cp3ub26 National Semiconductor Corporation, cp3ub26 Datasheet - Page 127

• Manufacturer Part Number: cp3ub26
• Description: Reprogrammable Connectivity Processor With Usb And Can Interfaces
• Manufacturer: National Semiconductor Corporation

18.10.6 CAN Global Configuration Register (CGCR)
The CAN Global Configuration Register (CGCR) is a 16-bit
wide register used to:
! Enable/disable the CAN module.
! Configure the BUFFLOCK function for the message buff-
! Enable/disable the time stamp synchronization.
! Set the logic levels of the CAN Input/Output pins, CAN-
! Choose the data storage direction (DDIR).
! Select the error interrupt type (EIT).
! Enable/disable diagnostic functions.
CANEN
CTX
CRX
BUFFLOCK The Buffer Lock bit configures the buffer lock
IGNACK LO DDIR
15
er 0..14.
RX and CANTX.
Reserved
7
6
12
The CAN Enable bit enables/disables the
CAN module. When the CAN module is dis-
abled, all internal states and the TEC and
REC counter registers are cleared. In addition
the CAN module clock is disabled. All CAN
module control registers and the contents of
the object memory are left unchanged. Soft-
ware must make sure that no message is
pending for transmission before the CAN
module is disabled.
0 – CAN module is disabled.
1 – CAN module is enabled.
The Control Transmit bit configures the logic
level of the CAN transmit pin CANTX.
0 – Dominant state is 0; recessive state is 1.
1 – Dominant state is 1; recessive state is 0.
The Control Receive bit configures the logic
level of the CAN receive pin CANRX.
0 – Dominant state is 0; recessive state is 1.
1 – Dominant state is 1; recessive state is 0.
function. If this feature is enabled, a buffer will
be locked upon a successful frame reception.
The buffer will be unlocked again by writing
RX_READY in the buffer status register, i.e.,
after reading data.
0 – Lock function is disabled for all buffers.
1 – Lock function is enabled for all buffers.
5
EIT DIAGEN INTERNAL LOOPBACK
11
PEN
TST
4
10
R/W
R/W
LOCK
0
0
BUFF
3
CRX CTX CANEN
9
2
1
8
0
127
TSTPEN
DDIR
The Time Sync Enable bit enables or disables
the time stamp synchronization function of the
CAN module.
0 – Time synchronization disabled. The Time
1 – Time synchronization enabled. The Time
The Data Direction bit selects the direction the
data bytes are transmitted and received. The
CAN module transmits and receives the CAN
Data1 byte first and the Data8 byte last
(Data1, Data2,...,Data7, Data8). If the DDIR
bit is clear, the data contents of a received
message is stored with the first byte at the
highest data address and the last data at the
lowest data address (see Figure 51). The
same applies for transmitted data.
0 – First byte at the highest address, subse-
1 – First byte at the lowest address, subse-
Stamp counter value is not reset upon re-
ception or transmission of a message to/
from buffer 0.
Stamp counter value is reset upon recep-
tion or transmission of a message to/from
buffer 0.
quent bytes at lower addresses.
quent bytes at higher addresses.
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