cp3ub26 National Semiconductor Corporation, cp3ub26 Datasheet - Page 56

• Manufacturer Part Number: cp3ub26
• Description: Reprogrammable Connectivity Processor With Usb And Can Interfaces
• Manufacturer: National Semiconductor Corporation

www.national.com
11.9
Table 23 lists the clock and reset registers.
11.9.1
The CRCTRL register is a byte-wide read/write register that
controls the clock selection and contains the power-on reset
status bit. At reset, the CRCTRL register is initialized as de-
scribed below:
SCLK
FCLK
PLLPWD
Reserved
7
CRCTRL
PRSFC
PRSSC
PRSAC
Name
6
Clock and Reset Control Register (CRCTRL)
CLOCK AND RESET REGISTERS
Table 23 Clock and Reset Registers
POR ACE2 ACE1 PLLPWD FCLK SCLK
The Slow Clock Select bit controls the clock
source used for the Slow Clock.
0
1
The Fast Clock Select bit selects between the
12 MHz Main Clock and the PLL as the source
used for the System Clock. After reset, the
Main Clock is selected. Attempting to switch to
the PLL while the PLLPWD bit is set (PLL is
turned off) is ignored. Attempting to switch to
the PLL also has no effect if the PLL output
clock has not stabilized.
0
1
The PLL Power-Down bit controls whether the
PLL is active or powered down (Stop PLL sig-
nal asserted). When this bit is set, the on-chip
PLL stays powered-down. Otherwise it is pow-
ered-up or it can be controlled by the Power
Management Module, respectively. Before
software can power-down the PLL in Active
mode by setting the PLLPWD bit, the FCLK bit
must be set. Attempting to set the PLLPWD
bit while the FCLK bit is clear is ignored. The
FCLK bit cannot be cleared until the PLL clock
has stabilized. After reset this bit is set.
0
1
5
–
–
–
–
–
–
Slow Clock driven by prescaled Main
Clock.
Slow Clock driven by 32.768 kHz oscilla-
tor.
The System Clock prescaler is driven by
the output of the PLL.
The System Clock prescaler is driven by
the 12-MHz Main Clock. This is the de-
fault after reset.
PLL is active.
PLL is powered down.
FF FC40h
FF FC42h
FF FC44h
FF FC46h
Address
4
3
High Frequency Clock
Low Frequency Clock
Prescaler Register
Prescaler Register
Prescaler Register
Clock and Reset
2
Control Register
Auxiliary Clock
Description
1
0
56
ACE1
ACE2
POR
11.9.2
The PRSFC register is a byte-wide read/write register that
holds the 4-bit clock divisor used to generate the high-fre-
quency clock. In addition, the upper three bits are used to
control the operation of the PLL. The register is initialized to
4Fh at reset (except in PROG mode
FCDIV
MODE
Res
7
High Frequency Clock Prescaler Register
(PRSFC)
6
When the Auxiliary Clock Enable bit is set and
a stable Main Clock is provided, the Auxiliary
Clock 1 prescaler is enabled and generates
the first Auxiliary Clock. When the ACE1 bit is
clear or the Main Clock is not stable, Auxiliary
Clock 1 is stopped. Auxiliary Clock 1 is used
as the clock input for the Advanced Audio In-
terface. After reset this bit is clear.
0
1
When the Auxiliary Clock Enable 2 bit is set
and a stable Main Clock is provided, the Aux-
iliary Clock 2 prescaler is enabled and gener-
ates Auxiliary Clock 2. When the ACE2 bit is
clear or the Main Clock is not stable, the Aux-
iliary Clock 2 is stopped. Auxiliary Clock 2 is
used as the clock input for the CVSD/PCM
transcoder and the A/D converter. After reset
this bit is clear.
0
1
The Power-On-Reset bit is set when a power-
turn-on condition has been detected. This bit
can only be cleared by software, not set. Writ-
ing a 1 to this bit will be ignored, and the pre-
vious value of the bit will be unchanged.
0
1
The Fast Clock Divisor specifies the divisor
used to obtain the high-frequency System
Clock from the PLL or Main Clock. The divisor
is (FCDIV + 1).
The PLL MODE field specifies the operation
mode of the on-chip PLL. After reset the
MODE bits are initialized to 100b, so the PLL
is configured to generate a 48-MHz clock.
This register must not be modified when the
System Clock is derived from the PLL Clock.
The System Clock must be derived from the
MODE
–
–
–
–
–
–
Auxiliary Clock 1 is stopped.
Auxiliary Clock 1 is active if the Main
Clock is stable.
Auxiliary Clock 2 is stopped.
Auxiliary Clock 2 is active if the Main
Clock is stable.
Software cleared this bit.
Software has not cleared his bit since the
last reset.
4
3
.)
FCDIV
0