st92f120 STMicroelectronics, st92f120 Datasheet - Page 96

• Manufacturer Part Number: st92f120
• Description: 8/16-bit Flash Mcu Family With Ram, Eeprom And J1850 Blpd
• Manufacturer: STMicroelectronics

ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.3 CLOCK MANAGEMENT
The various programmable features and operating modes of the CCU are handled by four registers:
– MODER (Mode Register)
– CLKCTL (Clock Control Register)
Figure 44. Clock Control Unit Programming
n
96/324
9
This is a System Register (R235, Group E).
The input clock divide-by-two and the CPU clock
prescaler factors are handled by this register.
This is a Paged Register (R240, Page 55).
The low power modes and the interpretation of
the HALT instruction are handled by this register.
(CLK_FLAG)
(available only if mapped on ext. pin)
XTSTOP
oscillator
Quartz
CK_AF
source
Wait for Interrupt and Low Power Modes:
LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode.
WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode.
XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected.
CLOCK1
CK_AF
1/2
(MODER)
DIV2
0
1
CLOCK2
6/8/10/14
MX(1:0)
PLL
x
(PLLCONF)
1/16
DX(2:0)
1/N
– CLK_FLAG (Clock Flag Register)
– PLLCONF (PLL Configuration Register)
This is a Paged Register (R242, Page 55).
This register contains various status flags, as
well as control bits for clock selection.
This is a Paged Register (R246, Page 55).
The PLL multiplication and division factors are
programmed in this register.
CSU_CKSEL
(CLK_FLAG)
0
1
XT_DIV16
0
1
1/4
(CLK_FLAG)
CKAF_SEL
(CLKCTL)
CKAF_ST
0
1
CPU Clock Prescaler
CLK_128
Peripherals
INTCLK
and P6.5
to