st92f120 STMicroelectronics, st92f120 Datasheet - Page 160

• Manufacturer Part Number: st92f120
• Description: 8/16-bit Flash Mcu Family With Ram, Eeprom And J1850 Blpd
• Manufacturer: STMicroelectronics

MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3 Input Pin Assignment
The two external inputs (TxINA and TxINB) of the
timer can be individually configured to catch a par-
ticular external event (i.e. rising edge, falling edge,
or both rising and falling edges) by programming
the two relevant bits (A0, A1 and B0, B1) for each
input in the external Input Control Register
(T_ICR).
The 16 different functional modes of the two exter-
nal inputs can be selected by programming bits
IN0 - IN3 of the T_ICR, as illustrated in
Table 32. Input Pin Function
Some choices relating to the external input pin as-
signment are defined in conjunction with the RM0
and RM1 bits in TMR.
For input pin assignment codes which use the in-
put pins as Trigger Inputs (except for code 1010,
Trigger Up:Trigger Down), the following conditions
apply:
160/324
9
IN3-IN0 bits
I C Reg.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TxINA Input
Trigger Up
Autodiscr.
Ext. Clock
Function
Clock Up
Up/Down
Up/Down
not used
not used
not used
Trigger
Trigger
Trigger
Trigger
Gate
Gate
Gate
Trigger Down
TxINB Input
Clock Down
Ext. Clock
Ext. Clock
Ext. Clock
Autodiscr.
Ext. Clock
Function
not used
not used
not used
not used
Trigger
Trigger
Trigger
Trigger
Gate
Figure 2
– a trigger signal on the TxINA input pin performs
– a trigger signal on the TxINB input pin always
Note: For proper operation of the External Input
pins, the following must be observed:
– the minimum external clock/trigger pulse width
– the minimum external clock/trigger pulse width
– the minimum delay between two clock/trigger
– the minimum gate pulse width must be at least
– in Autodiscrimination mode, the minimum delay
– if a number, N, of external pulses must be count-
an U/D counter load if RM0 is reset, or an exter-
nal capture if RM0 is set.
performs an external capture on REG1R. The
TxINB input pin is disabled when the Bivalue
Mode is set.
must not be less than the system clock (INTCLK)
period if the input pin is programmed as rising or
falling edge sensitive.
must not be less than the prescaler clock period
(INTCLK/3) if the input pin is programmed as ris-
ing and falling edge sensitive (valid also in Auto
discrimination mode).
pulse active edges must be greater than the
prescaler clock period (INTCLK/3), while the
minimum delay between two consecutive clock/
trigger pulses must be greater than the system
clock (INTCLK) period.
twice the prescaler clock period (INTCLK/3).
between the input pin A pulse edge and the edge
of the input pin B pulse, must be at least equal to
the system clock (INTCLK) period.
ed using a Compare Register in External Clock
mode, then the Compare Register must be load-
ed with the value [X +/- (N-1)], where X is the
starting counter value and the sign is chosen de-
pending on whether Up or Down count mode is
selected.