st92f120 STMicroelectronics, st92f120 Datasheet - Page 228

• Manufacturer Part Number: st92f120
• Description: 8/16-bit Flash Mcu Family With Ram, Eeprom And J1850 Blpd
• Manufacturer: STMicroelectronics

I2C BUS INTERFACE
I
Bit 0 = ITE Interrupt Enable.
The ITE bit enables the generation of interrupts.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(I2CCR.PE=0).
0: Interrupts disabled (reset value)
1: Interrupts enabled after any of the following con-
SCL is held low when the ADDTX flag of the
I2CSR2 register or the ADD10, SB, BTF or ADSL
flags of I2CSR1 register are set (See
when the DMA is not complete.
The transfer is suspended in all cases except
when the BTF bit is set and the DMA is enabled. In
this case the event routine must suspend the DMA
transfer if it is required.
228/324
9
2
C BUS INTERFACE (Cont’d)
ditions:
– Byte received or to be transmitted
– Address matched in Slave mode while
– Start condition generated
– No acknowledge received after byte transmis-
– Stop detected in Slave mode
– Arbitration lost in Master mode
– Bus error, Start or Stop condition detected
– Master has sent header byte
– Address byte successfully transmitted in Mas-
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
(I2CSR1.SB and I2CSR1.EVF flags = 1)
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
ter mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX = 1)
Figure
3) or
I
R241 - Read Only
Register Page: 20
Reset Value: 0000 0000 (00h)
Note: Some bits of this register are reset by a read
operation of the register. Care must be taken when
using instructions that work on single bit. Some of
them perform a read of all the bits of the register
before modifying or testing the wanted bit. So oth-
er bits of the register could be affected by the op-
eration.
In the same way, the test/compare operations per-
form a read operation.
Moreover, if some interrupt events occur while the
register is read, the corresponding flags are set,
and correctly read, but if the read operation resets
the flags, no interrupt request occurs.
Bit 7 = EVF Event Flag.
This bit is set by hardware as soon as an event (
listed below or described in
cleared by software when all event conditions that
set the flag are cleared. It is also cleared by hard-
ware
(I2CCR.PE=0).
0: No event
1: One of the following events has occurred:
2
EVF
C STATUS REGISTER 1 (I2CSR1)
7
– Byte received or to be transmitted
– Address matched in Slave mode while
– Start condition generated
– No acknowledge received after byte transmis-
– Stop detected in Slave mode
– Arbitration lost in Master mode
– Bus error, Start or Stop condition detected
– Master has sent header byte
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
(I2CSR1.SB and I2CSR1.EVF flags = 1)
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
ADD10
when
TRA
the
BUSY
interface
BTF
Figure
ADSL
3) occurs. It is
is
M/SL
disabled
SB
0