st92f120 STMicroelectronics, st92f120 Datasheet - Page 217

• Manufacturer Part Number: st92f120
• Description: 8/16-bit Flash Mcu Family With Ram, Eeprom And J1850 Blpd
• Manufacturer: STMicroelectronics

I
Figure 105. I
10.7.3 Functional Description
Refer to the I2CCR, I2CSR1 and I2CSR2 registers
in
The I
between the ST9 microcontroller and the I
protocol. In addition to receiving and transmitting
data, the interface converts data from serial to
parallel format and vice versa using an interrupt or
polled handshake.
It operates in Multimaster/slave I
lection of the operating mode is made by software.
The I
data pin (SDA) and a clock pin (SCL) which must
be configured as open drain when the I
enabled by programming the I/O port bits and the
PE bit in the I2CCR register. In this case, the value
of the external pull-up resistance used depends on
the application.
When the I
ports revert to being standard I/O port pins.
2
C BUS INTERFACE (Cont’d)
Section
2
2
C interface is connected to the I
C interface works as an I/O interface
SCL
SDA
0.1.7. for the bit definitions.
2
C cell is disabled, the SDA and SCL
2
C Interface Block Diagram
DMA
CONTROL
CONTROL
CLOCK
DATA
CONTROL SIGNALS
2
C mode. The se-
2
C bus by a
2
C cell is
2
C bus
LOGIC AND INTERRUPT/DMA REGISTERS
CLOCK CONTROL REGISTER
OWN ADDRESS REGISTER 1
OWN ADDRESS REGISTER 2
GENERAL CALL ADDRESS
DATA SHIFT REGISTER
CONTROL REGISTER
STATUS REGISTER 1
STATUS REGISTER 2
The I
Six of them are used for initialization:
– Own Address Registers I2COAR1, I2COAR2
– General Call Address Register I2CADR
– Clock Control Registers I2CCCR, I2CECCR
– Control register I2CCR
The following four registers are used during data
transmission/reception:
– Data Register I2CDR
– Control Register I2CCR
– Status Register 1 I2CSR1
– Status Register 2 I2CSR2
DATA BUS
DATA REGISTER
COMPARATOR
2
C interface has sixteen internal registers.
INTERRUPT
I2C BUS INTERFACE
VR02119A
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