IDT72V7250L10BB IDT, Integrated Device Technology Inc, IDT72V7250L10BB Datasheet - Page 4

• Manufacturer Part Number: IDT72V7250L10BB
• Description: IC FIFO 4096X36 10NS 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V7250L10BB

• Function: Asynchronous, Synchronous
• Memory Size: 147K (4K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 6.5ns
• Word Size: 72b
• Organization: 2Kx72
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V7250L10BB

TABLE 1 — — — — — BUS-MATCHING CONFIGURATION MODES
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The
mode desired is configured during master reset by the state of the Programmable
Flag Mode (PFM) pin.
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
to Figure 18 and 19 for Zero Latency Retransmit Timing.
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
During Master Reset (MRS) the following events occur: the read and write
The Partial Reset (PRS) also sets the read and write pointers to the first
It is also possible to select the timing mode of the PAE (Programmable Almost-
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
The Retransmit function allows data to be reread from the FIFO more than
If zero latency retransmit operation is selected, the first data word to be
Refer to Figure 16 and 17 for Retransmit Timing with normal latency. Refer
BM
H
H
H
H
L
IW
H
H
X
L
L
OW
H
H
X
L
L
4
shown in Table 1.
useful when the FIFO is used in Bus-Matching mode, to determine order of the
words. As an example, if Big-Endian mode is selected, then the most significant
word of the long word written into the FIFO will be read out of the FIFO first,
followed by the least significant word. If Little-Endian format is selected, then the
least significant word of the long word written into the FIFO will be read out first,
followed by the most significant word. The mode desired is configured during
master reset by the state of the Big-Endian (BE) pin.
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D8 during the parallel
programming of the flag offsets. If Non-Interspersed Parity mode is selected,
then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode
is selected during Master Reset by the state of the IP input pin.
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read
Chip Select is synchronized to the RCLK. Both the output enable and read chip
select control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
72V7290/72V72100 are fabricated using IDT’s high speed submicron CMOS
technology.
The device can be configured with different input and output bus widths as
A Big-Endian/Little-Endian data word format is provided. This function is
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
If, at any time, the FIFO is not actively performing an operation, the chip will
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
JTAG test pins are also provided, the FIFO has fully functional Boundary
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
Write Port Width
TM
FIFO
x72
x36
x18
x72
x72
COMMERCIAL TEMPERATURE RANGE
Read Port Width
x72
x72
x72
x36
x18