IDT72V7250L10BB IDT, Integrated Device Technology Inc, IDT72V7250L10BB Datasheet - Page 37

• Manufacturer Part Number: IDT72V7250L10BB
• Description: IC FIFO 4096X36 10NS 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V7250L10BB

• Function: Asynchronous, Synchronous
• Memory Size: 147K (4K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 6.5ns
• Word Size: 72b
• Organization: 2Kx72
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V7250L10BB

Q
NOTES:
1. OE = LOW; RCS = LOW.
D
WCLK
RCLK
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
WCLK
WEN
0
0
REN
PAF
WEN
RCLK
In IDT Standard mode: D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for the IDT72V7260 and 8,192 for the IDT72V7270, 16,384 for
the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT mode: D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
- Q
- D
REN
LD
LD
n
16
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKL
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
DATA IN OUTPUT REGISTER
t
ENH
t
CLKH
t
CLKH
1
(2)
t
CLK
t
SKEW2
CLK
t
t
ENS
LDS
t
t
CLKL
DS
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
t
ENS
LDS
t
CLKL
OFFSET
PAE
2
t
PAFS
37
t
t
t
ENH
DH
LDH
t
t
LDH
t
t
ENH
ENS
A
t
SKEW2
TM
(3)
FIFO
OFFSET
PAF
PAE OFFSET
t
ENH
D - m words in FIFO
1
t
t
t
COMMERCIAL TEMPERATURE RANGE
DH
LDH
ENH
t
t
ENH
LDH
t
A
(2)
2
PAFS
t
PAFS
PAF OFFSET
). If the time between the
D-(m+1) words
in FIFO
4680 drw 28
4680 drw27
4680 drw26
(2)