IDT72V7250L10BB IDT, Integrated Device Technology Inc, IDT72V7250L10BB Datasheet - Page 18

• Manufacturer Part Number: IDT72V7250L10BB
• Description: IC FIFO 4096X36 10NS 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V7250L10BB

• Function: Asynchronous, Synchronous
• Memory Size: 147K (4K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 6.5ns
• Word Size: 72b
• Organization: 2Kx72
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V7250L10BB

flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,
LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
A HIGH will select Interspersed Parity mode. The IP bit function allows the user
to select the parity bit in the long word loaded into the parallel port (D
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bits are located in bit position D
D
Non-Interspersed Parity mode is selected, then D
to be valid bits and D
IP mode is selected during Master Reset by the state of the IP input pin.
OUTPUTS:
FULL FLAG ( FF/IR )
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the
IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384
for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the
IDT72V72100). See Figure10, Write Cycle and Full Flag Timing (IDT
Standard Mode), for the relevant timing information.
when memory space is available for writing in data. When there is no longer
any free space left, IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either MRS or PRS), IR will go HIGH after D writes
to the FIFO (D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049
for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270,
16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the
IDT72V72100). See Figure 13, Write Timing (FWFT Mode), for the relevant
timing information.
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
double register-buffered outputs.
EMPTY FLAG ( EF/OR )
function is selected. When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty. See Figure 11,
Read Cycle, Output Enable, Empty Flag and First Word Latency Timing (IDT
Standard Mode), for the relevant timing information.
at the same time that the first word written to an empty FIFO appears valid on
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
44
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.
, D
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
The IR status not only measures the contents of the FIFO memory, but also
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
53
, D
62
and D
71
64
during the parallel programming of the flag offsets. If
, D
65
, D
66,
D
67
, D
68
, D
69
8
, D
, D
17
70
and D
and D
28
8
71
are is assumed
, D
are ignored.
17
0
-Dn) when
, D
26
, D
35,
18
the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts
the last word from the FIFO memory to the outputs. OR goes HIGH only with
a true read (RCLK with REN = LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited until OR goes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (512-m) writes for the IDT72V7230,
(1,024-m) writes for the IDT72V7240, (2,048-m) writes for the IDT72V7250,
(4,096-m) writes for the IDT72V7260, (8,192-m) writes for the IDT72V7270,
(16,384-m) writes for the IDT72V7280, (32,768-m) writes for the IDT72V7290,
and (65,536-m) writes for the IDT72V72100. The offset “m” is the full offset value.
The default setting for this value is stated in the footnote of Table 1.
(1,025-m) writes for the IDT72V7240, (2,049-m) writes for the IDT72V7250,
(4,097-m) writes for the IDT72V7260 and (8,193-m) writes for the IDT72V7270,
(16,385-m) writes for the IDT72V7280, (32,769-m) writes for the IDT72V7290
and (65,537-m) writes for the IDT72V72100, where “m” is the full offset value.
The default setting for this value is stated in Table 2.
Standard and FWFT Modes), for the relevant timing information.
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 25, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Modes).
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
in the FIFO. The default setting for this value is stated in Table 2.
(IDT Standard and FWFT Modes), for the relevant timing information.
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Modes).
HALF-FULL FLAG ( HF )
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
In FWFT mode, the PAF will go LOW after (513-m) writes for the IDT72V7230,
See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT
See Figure 24, Synchronous Programmable Almost-Empty Flag Timing
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
If asynchronous PAF configuration is selected, the PAF is asserted LOW
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less
If asynchronous PAE configuration is selected, the PAE is asserted LOW
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
EF/OR is synchronous and updated on the rising edge of RCLK.
TM
FIFO
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