IDT72V7250L10BB IDT, Integrated Device Technology Inc, IDT72V7250L10BB Datasheet

IC FIFO 4096X36 10NS 256BGA

IDT72V7250L10BB

Manufacturer Part Number
IDT72V7250L10BB
Description
IC FIFO 4096X36 10NS 256BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V7230L15BB.pdf (42 pages)

Specifications of IDT72V7250L10BB

Function
Asynchronous, Synchronous
Memory Size
147K (4K x 36)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Configuration
Dual
Density
144Kb
Access Time (max)
6.5ns
Word Size
72b
Organization
2Kx72
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
75mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V7250L10BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
BOSTOCK HK LIMITED BOSTOCK HK LIMITED
Part Number:
IDT72V7250L10BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES:
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
Choose among the following memory organizations:
100 MHz operation (10 ns read/write cycle time)
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable word representation
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100 ⎯ ⎯ ⎯ ⎯ ⎯ 65,536 x 72
TRST
MRS
PRS
TDO
TMS
TCK
TDI
OW
BM
BE
IW
IP
⎯ ⎯ ⎯ ⎯ ⎯ 512 x 72
⎯ ⎯ ⎯ ⎯ ⎯ 1,024 x 72
⎯ ⎯ ⎯ ⎯ ⎯ 2,048 x 72
⎯ ⎯ ⎯ ⎯ ⎯ 4,096 x 72
⎯ ⎯ ⎯ ⎯ ⎯ 8,192 x 72
⎯ ⎯ ⎯ ⎯ ⎯ 16,384 x 72
⎯ ⎯ ⎯ ⎯ ⎯ 32,768 x 72
(BOUNDARY SCAN)
CONFIGURATION
WRITE CONTROL
WRITE POINTER
WEN
CONTROL
CONTROL
RESET
LOGIC
LOGIC
LOGIC
JTAG
BUS
WCLK
3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
OE
OUTPUT REGISTER
D
INPUT REGISTER
Q
0
0
-D
-Q
RAM ARRAY
n
16,384 x 72
32,768 x 72
65,536 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
n
512 x 72
(x72, x36 or x18)
(x72, x36 or x18)
1
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Asynchronous operation of Output Enable, OE
Read Chip Select ( RCS ) on Read Side
Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
Features JTAG (Boundary Scan)
High-performance submicron CMOS technology
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
OFFSET REGISTER
READ POINTER
LOGIC
CONTROL
FLAG
LOGIC
READ
LD
SEN
IDT72V7290, IDT72V72100
REN
RCLK
RCS
IDT72V7230, IDT72V7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
SCLK
4680 drw01
RT
RM
JANUARY 2009
EF/OR
PAE
FF/IR
PAF
HF
FWFT/SI
PFM
FSEL0
FSEL1
DSC-4680/11

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IDT72V7250L10BB Summary of contents

Page 1

VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72 FEATURES: • • • • • Choose among the ...

Page 2

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 DESCRIPTION: The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100 are exceptionally deep, high speed, CMOS ...

Page 3

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 DESCRIPTION (CONTINUED) and Read Enable (REN) input. Data is read ...

Page 4

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 During Master Reset (MRS) the following events occur: the read ...

Page 5

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 PIN DESCRIPTION Symbol Name I/O D –D Data Inputs I ...

Page 6

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 PIN DESCRIPTION (CONTINUED) Symbol Name I/O EF/OR Empty Flag/ O ...

Page 7

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with ...

Page 8

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.15V, T ...

Page 9

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL ...

Page 10

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 TABLE 2 — — — — — DEFAULT PROGRAMMABLE FLAG ...

Page 11

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K FIFO COMMERCIAL TEMPERATURE RANGE 11 ...

Page 12

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K WEN REN ...

Page 13

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 1st Parallel Offset Write/Read Cycle D/Q71 D/Q19 D/Q17 EMPTY OFFSET ...

Page 14

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 FUNCTIONAL DESCRIPTION (CONTINUED) SERIAL PROGRAMMING MODE If Serial Programming mode ...

Page 15

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K FWFT mode is selected, the FIFO will mark the ...

Page 16

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 SIGNAL DESCRIPTION INPUTS: DATA ...

Page 17

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K will go HIGH allowing a write to occur. The ...

Page 18

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM, ...

Page 19

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K IDT Standard mode reads are performed after ...

Page 20

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: ...

Page 21

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: ...

Page 22

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 JTAG TIMING SPECIFICATION TCK TDI/ TMS ...

Page 23

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and ...

Page 24

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K Test-Logic 0 Run-Test/ Input = TMS NOTES: 1. Five ...

Page 25

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 THE INSTRUCTION REGISTER The Instruction register allows an instruction to ...

Page 26

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 MRS t RSS REN t RSS WEN t RSS FWFT/SI ...

Page 27

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 PRS t RSS REN t RSS WEN t RSS RT ...

Page 28

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K WRITE WCLK 1 (1) t SKEW1 ...

Page 29

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 RCLK t ENS REN t t RCSH RCSS RCS EF ...

Page 30

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K FIFO COMMERCIAL TEMPERATURE RANGE 30 ...

Page 31

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K FIFO COMMERCIAL TEMPERATURE RANGE 31 ...

Page 32

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K FIFO COMMERCIAL TEMPERATURE RANGE 32 ...

Page 33

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 RCLK t t ENH ENS t RTS REN t A ...

Page 34

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 RCLK t ENH t ENS t RTS REN Q - ...

Page 35

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 RCLK t ENS REN ...

Page 36

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 RCLK t ENS REN ...

Page 37

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 WCLK LD WEN Figure 21. ...

Page 38

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K CLKH CLKL WCLK t ENS t ENH WEN ...

Page 39

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K CLKH WCLK WEN n words in FIFO PAE n ...

Page 40

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased ...

Page 41

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II 512 36, 16K x 72, 32K x 72, 64K x 72 FWFT/SI FWFT/SI WRITE CLOCK WCLK IDT 72V7230 WRITE ENABLE WEN ...

Page 42

ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 06/01/2000 pgs 33, 34, 34, 35, 38, 41, and 42. 11/01/2000 pgs ...

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