USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 42

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

SMSC DS – USB97C100
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
(0x7F60 - RESET=0x55)
(0x7F61 - RESET=0x55)
EP3TX_EMPTY
EP2TX_EMPTY
EP1TX_EMPTY
EP0TX_EMPTY
EP7TX_EMPTY
EP6TX_EMPTY
EP5TX_EMPTY
EP3TX_FULL
EP2TX_FULL
EP1TX_FULL
EP0TX_FULL
EP7TX_FULL
EP6TX_FULL
EP5TX_FULL
TXSTAT_A
STAT_B
NAME
NAME
Table 71 - Transmit FIFO Status Register B
Table 70 - Transmit FIFO Status Register A
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Endpoint 3 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 2 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 1 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 0 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 7 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 6 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 5 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Page 42
TRANSMIT FIFO STATUS REGISTER A
TRANSMIT FIFO STATUS REGISTER B
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001