EMC2102 Standard Microsystems Corporation, EMC2102 Datasheet
EMC2102
Available stocks
Related parts for EMC2102
EMC2102 Summary of contents
Page 1
... CPU substrate thermal diodes on multiple process geometries as well as with discrete diode-connected transistors. Both Beta Compensation and REC can be disabled on the EMC2102 to maintain accuracy when monitoring AMD thermal diodes. The EMC2102 includes a closed-loop RPM based Fan Control Algorithm that integrates a linear fan driver capable of sourcing 600mA of current ...
Page 2
... EMC2102-DZK FOR 28-PIN QFN LEAD-FREE ROHS COMPLIANT PACKAGE (ADDRESS - 011_1101) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
Page 3
... RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table of Contents Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Pin Layout for EMC2102 2.2 Pin Description for EMC2102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 4 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 ...
Page 4
... Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.18 TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.19 TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.20 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.21 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Appendix A TACH Reading Table - 2000 RPM Range Appendix B TACH Reading Table - 500RPM Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Revision 1.95 (10-19-06) RPM-Based Fan Controller with HW Thermal Shutdown 4 DATASHEET Datasheet SMSC EMC2102 ...
Page 5
... Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5.1 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5.2 FAN_MODE Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5.3 CLK_SEL Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5.4 SHDN_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6.1 EMC2102 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6.2 Temperature data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.4 Critical/Thermal Shutdown Temperature Register Table 6.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6 ...
Page 6
... Figure 2.1 EMC2102 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4.1 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5.1 EMC2102 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 5.2 RPM based Fan Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 5.3 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 5.4 EMC2102 Critical/Thermal Shutdown Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 5.5 HW_SHDN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 5.6 5V Reset Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 7.1 EMC2102 28-Pin 5x5mm QFN Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . 46 Revision 1.95 (10-19-06) ...
Page 7
... Ext Temp Limit Registers 11 bit Σ Δ Ext. Temp Registers ADC Voltage Reading Bandgap Reference Voltage -> Temperature Converison Automatic Fan Control Algorithms TACH Monitor Figure 1.1 EMC2102 Block Diagram 7 DATASHEET SMCLK SMBus Slave SMDATA Protocol ALERT# POWER_OK Register Set and Logic FAN_MODE Revision 1.95 (10-19-06) ...
Page 8
... Chapter 2 Pinout 2.1 Pin Layout for EMC2102 1 VDD_3V 2 DN1 DP1 3 DN2 4 DP2 5 DN3 6 DP3 7 Revision 1.95 (10-19-06) RPM-Based Fan Controller with HW Thermal Shutdown EMC2102 QFN Figure 2.1 EMC2102 Pin Diagram 8 DATASHEET Datasheet 21 N/C 20 GND ALERT# 19 CLK_IN 18 CLK_SEL 17 16 RESET# 15 N/C SMSC EMC2102 ...
Page 9
... RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 2.2 Pin Description for EMC2102 PIN NAME 1 VDD_3V 2 DN1 3 DP1 4 DN2 5 DP2 6 DN3 7 DP3 8 N/C 9 SHDN_SEL 10 FAN_MODE 11 TRIP_SET 12 SYS_SHDN# 13 THERMTRIP# 14 POWER_OK 15 N/C 16 RESET# 17 CLK_SEL 18 CLK_IN 19 ALERT# 20 GND 21 N/C 22 SMDATA 23 SMCLK SMSC EMC2102 Table 2.1 Pin Description FUNCTION Supply Connection of 3 ...
Page 10
... Linear fan drive signal. Both FAN pins should be connected together. 5V supply input for the linear fan driver. Both VDD_5V pins should be connected to same 5V supply. Input from the tachometer pin of the fan. 10 DATASHEET Datasheet TYPE Power AO AO Power DI (5V) SMSC EMC2102 ...
Page 11
... Supply Voltage V DD_3V 5V Supply Voltage V DD_5V Supply Current from I DD3 VDD_3V pin Supply Current from I DD5 VDD_5V pin SMSC EMC2102 Table 3.1 Absolute Maximum Ratings Table 2.1) -0.3 to 6.5 -0 -0.3 to VDD_5V + 0.3 -0.3 to VDD_3V + 0.3 0 125 -55 to 150 2000 ) is dependent on the design of the thermal vias. Without thermal JA is approximately 60° ...
Page 12
... AMD diode (Note 3.5) Connected across CPU or GPU thermal diode (Note 3.5) Series resistance in DP and DN lines (Note 3 rising edge DD_5V 3V < V < 3.6V DD_3V I = 600mA, VDD_5V = SOURCE 5V Momentary Current drive at startup for < 2 seconds Sourcing current, Thermal shutdown not triggered, FAN_OUT = 0V SMSC EMC2102 ...
Page 13
... Input Low Voltage V IL Input High/Low Current Input Capacitance C IN Output Low Sink Current Clock Frequency f SMB Spike Suppression t SP SMSC EMC2102 = 27°C unless otherwise noted. A MIN TYP MAX RPM Based Fan Controller 480 16000 ±1 ±2 ±5 ±7.5 Thermal Shutdown 150 50 ...
Page 14
... Capacitive Load C LOAD Revision 1.95 (10-19-06) RPM-Based Fan Controller with HW Thermal Shutdown = 0°C to 85° 27°C unless otherwise noted. A MIN TYP MAX UNITS 1.3 us 0.6 us 0 1.3 us 0.6 us 300 ns Min = 20+0.1C 300 ns Min = 20+0.1C 400 pF per bus line 14 DATASHEET Datasheet CONDITIONS ns LOAD ns LOAD SMSC EMC2102 ...
Page 15
... RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Chapter 4 System Management Bus Interface Protocol The EMC2102 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in however the EMC2102 will not stretch the clock signal ...
Page 16
... Table 4.4 Send Byte Protocol REGISTER WR ACK ADDRESS 1 1 Table 4.5. Table 4.5 Receive Byte Protocol RD ACK REGISTER DATA 1 1 Table 4.6. RD ACK ADDRESS DATASHEET Datasheet Table RD ACK Register NACK Data Table 4.4. ACK STOP NACK STOP DEVICE NACK STOP SMSC EMC2102 4.3. STOP 1 ...
Page 17
... RPM-Based Fan Controller with HW Thermal Shutdown Datasheet The EMC2102 will respond to the ARA command if the ALERT# pin has been asserted but will not immediately release the ALERT# pin. The ALERT# pin is released under the following conditions. 1. The Interrupt Status Registers are read and the error condition has been removed. ...
Page 18
... The EMC2102 integrates a closed-loop RPM based Fan Control Algorithm. A host writes the desired fan speed into a register of the EMC2102 via the SMBus and the integrated fan controller will maintain the fan at the desired speed using fan speed feedback from the TACH output from a 3-wire fan. The fan control algorithm controls an integrated 5V, 600mA, linear fan driver ...
Page 19
... SYS_SHDN THERMTRIP POWER_OK SMSC EMC2102 VDD_3V VDD_5V EMC2102 SMCLK SMDATA ALERT# TACH FAN DP1 DN1 DP2 DN2 DP3 DN3 CLK_SEL CLK_IN FAN_MODE SHDN_SEL TRIP_SET SYS_SHDN# RESET# THERMTRIP# POWER_OK Figure 5.1 EMC2102 System Diagram 19 DATASHEET 5V 3.3V TACHOMETER FAN VCC 3.3V 32.768KHz Clock 3.3V RESET Revision 1.95 (10-19-06) ...
Page 20
... Resistance Error Correction The EMC2102 includes active Resistance Error Correction to remove the effect 100 ohms of series resistance. Without this automatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. The error induced by parasitic resistance is approximately +0.7° ...
Page 21
... Datasheet 5.2 Fan Control Modes of Operation The EMC2102 has two modes of operation for the High Side Fan Driver. They are: 1. Manual Mode - in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver Setting Register (see The Manual Mode is enabled by clearing the EN bit in the Fan Configuration Register (see Section 6 ...
Page 22
... The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT# pin. The EMC2102 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The fan controller will function either with an externally supplied 32.768KHz clock source or with it’ ...
Page 23
... The RPM based Fan Control Algorithm powers-up enabled and active. The following registers control the algorithm. The EMC2102 fan control registers are preloaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements ...
Page 24
... For the remaining spin up time, the fan driver output is set a a user defined level (60% or 75% drive). After the Spin Up Routine has finished, the EMC2102 measures the TACH. If the measured TACH count is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan ...
Page 25
... Datasheet 5.3.4 FAN_MODE Pin The FAN_MODE pin is used to determine the fan driver output levels at power-up before the EMC2102 has been programmed. After power-up, the fan driver will be set at the selected drive until the RPM based Fan Control Algorithm is started or disabled. The level on the pin determines the function as shown in ...
Page 26
... High Side Fan Driver The EMC2102’s fan controller integrates a 5V, 600mA, linear high side fan driver to directly drive a 5V fan. By fully integrating the linear fan driver, the typical requirement for the discrete pass device and other external linearization circuitry is completely eliminated. The linear fan driver is driven by an 8-bit DAC providing better than 20mV resolution between steps ...
Page 27
... From the POWER_OK Power Supply ThermTrip# Power_OK ThermTrip_SHDN Figure 5.4 EMC2102 Critical/Thermal Shutdown Block Diagram SMSC EMC2102 Section 5.7.2. Section 5.7.1. Critical Shutdown Logic SYS1 - SYS3 Temperature SW_SHDN Conversion and Limit Registers ‘0’ or ‘open’ PIN Decode Temperature Conversion ‘ ...
Page 28
... The EMC2102 has one ‘strappable’ input (SHDN_SEL) allowing for configuration of the hardware Critical/Thermal Shutdown. This pin has 3 possible states and is monitored and decoded by the EMC2102 at power-up. The three possible states are 0 (tied to GND), 1 (tied to 3.3V) or High-Z (open). The states of this pin determine which remote temperature channel and configuration is used by the Critical/Thermal Shutdown function ...
Page 29
... TRIP_SET input pin (as shown in P consecutive measurements defined by the fault queue. If the HW_SHDN output is asserted and the temperature drops below T TP Temperature not defined HW_SHDN SMSC EMC2102 , then it will be set to a logic ‘0’ state. P Temperature Measurements End Exceeds TP th After 4 HW_SHDN set Figure 5 ...
Page 30
... Reset Controller The EMC2102 also provides a ‘power-good’ reset controller for the system’s 5V supply rail. The reset controller will set the RESET# pin to a logic ‘0’ after power-up and set the RESET# pin to a logic ‘1’ 220ms after the VDD_5V supply rises above its threshold voltage (see If the VDD_5V supply drops below the reset threshold, then the RESET# pin will be set to ‘ ...
Page 31
... External Diode 2 Beta Configuration 32h R/W External Diode REC Configuration SMSC EMC2102 Table 6.1 EMC2102 Register Set FUNCTION Temperature Registers Stores the integer data of the Internal Temp Reading Stores the integer data of External Diode 1 Stores the integer data of External Diode 2 Stores the integer data of External ...
Page 32
... Table 6.1 EMC2102 Register Set (continued) REGISTER ADDR R/W NAME 41h R/W External Diode 1 Temp High Limit 42h R/W External Diode 2 Temp High Limit 43h R/W External Diode 3 Temp High Limit 51h R/W Fan Driver Setting 52h R/W Fan Configuration 53h R/W Fan Spin Up Configuration 54h R/W Fan Step 55h ...
Page 33
... If the High Side Fan Driver is active, then self-heating of the large current drive device will affect the internal temperature reading. Therefore not recommended that the Internal temperature channel be used to monitor the ambient air temperature. SMSC EMC2102 Table 6.2 Temperature data Registers B6 B5 ...
Page 34
... Configuration QUEUE[1:0] The Configuration Register controls the basic functionality of the EMC2102. The bits are described below. The Configuration Register is software locked. Bit 7-6 - QUEUE[1:0] - determines how many consecutive out-of-limit errors must occur on the hardware selected and software enabled temperature channels before the SYS_SHDN# pin is ...
Page 35
... Bit CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the conversion rate and the average current will increase as the conversion rate increases. SMSC EMC2102 Section 5.7). ...
Page 36
... Status Register 1 The Interrupt Status Registers report the operating condition of the EMC2102. If any of the bits are set to a logic ‘1’ (other than the RESET pin) then the ALERT# pin will be asserted low. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT# pin will be released ...
Page 37
... Status Register 2 The Interrupt Status Registers report the operating condition of the EMC2102. If any of the bits (except the PWROK, THERM, and HWS bits) are asserted then the ALERT# pin will be asserted low. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT# pin will be released. Bit 7 - PWROK - this bit is set if the POWER_OK pin is set to a logic ‘ ...
Page 38
... The default setting is calibrated for 65nm CPU’s. For 90nm CPU’s the optimal beta setting is 04h. Revision 1.95 (10-19-06) RPM-Based Fan Controller with HW Thermal Shutdown Table 6.12 Beta Configuration Registers 5.4), the External Diode 1 Beta Configuration Register becomes read only. 38 DATASHEET Datasheet DEFAULT BETA1[2:0] 03h BETA2[2:0] 03h SMSC EMC2102 ...
Page 39
... REC functionality for External Diode 2 is enabled. Bit 0 - REC1 - Controls the Resistive Error Correction functionality of External Diode 1 ‘0’ - the REC functionality for External Diode 1 is disabled ‘1’ (default) - the REC functionality for External Diode 1 is enabled. SMSC EMC2102 ...
Page 40
... External Diode Sign 3 High Limit The EMC2102 contains high limits for all temperature channels.If any particular temperature channel exceeds the high limit then the appropriate status bit is set. Each temperature channel software limit can be individually enabled to assert the SYS_SHDN# pin if the temperature exceeds this limit. ...
Page 41
... Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table 6.19. SMSC EMC2102 LIMIT2K ...
Page 42
... Table 6.19 Update Time Table 6.21. Table 6.21 Spin Time DATASHEET Datasheet UPDATE TIME 100ms 200ms 300ms 400ms (default) 500ms 800ms 1200ms 1600ms DEFAULT LEVEL SPINUP_TIM 01h E [1:0] TOTAL SPIN UP TIME 250 ms 500 ms (default) SMSC EMC2102 ...
Page 43
... Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive level that cannot support fan operation. The Fan Minimum Drive Register is software locked. SMSC EMC2102 Table 6.21 Spin Time (continued Table 6 ...
Page 44
... DATASHEET Datasheet DEFAULT 128 F5h for translating the count to an RPM DEFAULT 128 FAh DEFAULT 128 FFh SMSC EMC2102 ...
Page 45
... The Product ID Register contains a unique 8 bit word that identifies the product. 6.21 Revision Register ADDRESS REGISTER B7 FFh Revision 0 The Revision Register contains a 8 bit word that identifies the die revision. SMSC EMC2102 1 sec COUNT = TACH Reading Register ⎛ ⎞ ⎛ ⎞ ) 32768 × ...
Page 46
... Chapter 7 Package Drawing Figure 7.1 EMC2102 28-Pin 5x5mm QFN Package Outline and Parameters Revision 1.95 (10-19-06) RPM-Based Fan Controller with HW Thermal Shutdown 46 DATASHEET Datasheet SMSC EMC2102 ...
Page 47
... SMSC EMC2102 Table A.1 TACH Reading Table - Limit2K = ‘1’ DEC HEX RPM 29 1D 16949 30 1E 16384 31 1F 15855 32 20 15360 33 21 14895 34 22 14456 35 ...
Page 48
... AA 2891 171 AB 2874 172 AC 2858 173 AD 2841 174 AE 2825 175 AF 2809 176 B0 2793 177 B1 2777 178 B2 2761 179 B3 2746 180 B4 2731 181 B5 2716 182 B6 2701 183 B7 2686 184 B8 2671 185 B9 2657 186 BA 2643 187 BB 2628 188 BC 2614 SMSC EMC2102 ...
Page 49
... D5 2308 214 D6 2297 215 D7 2286 216 D8 2276 217 D9 2265 218 DA 2255 219 DB 2244 220 DC 2234 SMSC EMC2102 Table A.1 TACH Reading Table - Limit2K = ‘1’ DEC HEX RPM 221 DD 2224 222 DE 2214 223 DF 2204 224 E0 2194 225 E1 2185 226 E2 2175 227 ...
Page 50
... SMSC EMC2102 ...
Page 51
... SMSC EMC2102 Table B.1 TACH Reading Table - Limit2K = ‘0’ DEC HEX RPM 124 7C 991 125 7D 983 126 7E 975 127 7F 968 128 80 960 129 81 953 130 ...
Page 52
... F3 506 244 F4 504 245 F5 502 246 F6 500 247 F7 497 248 F8 495 249 F9 493 250 FA 492 251 FB 490 52 DATASHEET Datasheet Table B.1 TACH Reading Table - Limit2K = ‘0’ DEC HEX RPM 252 FC 488 253 FD 486 254 FE 484 255 FF Disabled SMSC EMC2102 ...