USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 17

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

MCU REGISTER DESCRIPTION
MCU Runtime Registers
These bits are automatically cleared each time this register is read. Therefore, each time this register is read all
pending interrupts must be serviced before continuing normal operation.
Notes:
SMSC DS – USB97C100
TX_EMPTY is useful for warning of USB performance degradation. This interrupt indicates that the next time the
Host polls the affected endpoint, it will receive a NAK for that endpoint, thus reducing effective overall bandwidth
due to retries. Firmware must use TX_STAT A, B, and C to determine which endpoint queue is empty.
When ISADMA causes an interrupt, the 8237 CH_STAT register should also be read and serviced when the bit
causing the interrupt is to be rearmed. When ISR_0 is read and the ISADMA bit is cleared, any other low-to-high
transitions in the BUS_STAT register bits that are not masked will still cause an interrupt.
BIT
7
6
5
4
3
2
1
0
(0x7F00 - RESET=0x00)
TX_EMPTY
ISR_0
RX_PKT
TX_PKT
ISADMA
NAME
IRQ3
IRQ2
IRQ1
IRQ0
R/W
Table 9 - Interrupt 0 Source Register
R
R
R
R
R
R
R
R
External interrupt input.
0 = Inactive
1 = Active
External interrupt input.
0 = Inactive
1 = Active
External interrupt input.
0 = Inactive
1 = Active
External interrupt input.
0 = Inactive
1 = Active
1 = A Packet Number (PNR) has been successfully queued
on the RXFIFO.
1 = Whenever an enabled TX Endpoint's FIFO becomes
empty. This will occur when the last queued packet in one of
the 16 TX queues is successfully transferred to the Host.
1 = A Packet was successfully transmitted.
1 = When a selected 8237 channels in
BUS_STAT/BUS_MASK register pair either reached Terminal
Count or have a new DMA Request Pending.
Page 17
INTERRUPT 0 SOURCE REGISTER
DESCRIPTION
Rev. 01/03/2001