USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 37

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION
MMU Interface Registers
Notes:
Notes:
SMSC DS – USB97C100
The Read FIFO may take at most 1.218µs after the PNH is written to present valid data.
The Write FIFO may take at most 2.520µs after writing the last byte of data to the FIFO to finish writing that data
to the buffer.
The worst case sequential access times to the FIFOs while the 8237 is simultaneously arbitrating for the MMU,
and a USB packet is currently being transferred, is 588ns.
-
-
[7:0]
12MHz) before reading from this register. After waiting, the 8051, in auto-increment mode (PRH bit 6=1), can
read a byte every cycle (at up to 16MHz).
on every instruction cycle. After writing data, the 8051 should wait at least 3 instruction cycles (at 12MHz)
before changing the PNR or PRH :PRL registers for a Read . Again, after waiting 1.218µs, the 8051 can read
a byte every instruction cycle.
[7:0]
BIT
(READ) Therefore, after changing the PRH register, the 8051 should wait at least 2 instruction cycles (at
(WRITE) The data register mode can be switched to write at any time, and data can be written immediately
BIT
This register must be written before PRH.
The value read from this register is not necessarily what was last written to it, but actually the last address
used to access the buffer RAM.
MMU_DATA
[D7:D0]
(0x7F50)
(0x6000)
NAME
NAME
A[7:0]
PRL
R/W
R/W
R/W
R/W
Table 59 - MMU Data Window Register
Table 60 - Pointer Register (Low)
Data Packet Window.
When RCV in the PRH register = '1', this is the byte pointed to by
the packet number on the top of the RXFIFO, and the packet
offset of PRH:PRL.
When RCV in the PRH register = '0', this is the byte pointed to by
the packet number in the PNR register, and the packet offset of
PRH:PRL.
LSB of the (0-1277 Max) offset of the allocated Packet Pointed to
by PNR. The byte(s) pointed to by this register can be read and
written to by the MCU at 0x6000.
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MMU DATA WINDOW REGISTER
POINTER REGISTER (LOW)
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001