USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 19

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

SMSC DS – USB97C100
[7:0]
[7:0]
[7:0]
BIT
BIT
BIT
[7:5]
[7:0]
[7:0]
BIT
BIT
BIT
(0x7F12 - RESET=0xXX)
(0x7F14 - RESET=0xXX)
(0x7F10- RESET=0xXX)
4
3
2
1
0
(0x7F07- RESET=0x25)
(0x7F03- RESET=0xFF)
(0x7F06- RESET=0xXX)
GP_FIFO1
GP_FIFO2
GP_FIFO3
GP_FIFO1
GP_FIFO2
GP_FIFO3
PWR_MNG
RX_OVRN
HEX 0x25
Reserved
NAME
NAME
NAME
BCD '25'
ALLOC
NAME
DEV_REV
DEV_ID
EOT
SOF
Rev.
IMR_1
Table 14 - Device Identification Register
R/W
Table 13 - Device Revision Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Table 12 - Interrupt 1 Mask
Table 15– 8051 GP FIFO1
Table 16– 8051 GP FIFO2
Table 17– 8051 GP FIFO3
8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
This register defines additional revision information
used internally by SMSC
Reserved
EOT interrupt mask
0 = Enable Interrupt
1 = Mask Interrupt
Start of Frame Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
MCU Software Allocation Complete Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Receive Overrun Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Power Management Wakeup Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
This register defines additional revision information
used internally by SMSC. The value is silicon revision
dependent.
Page 19
DEVICE IDENTIFICATION REGISTER
INTERRUPT 1 MASK REGISTER
DEVICE REVISION REGISTER
DESCRIPTION
DESCRIPTION
DESCRIPTION
8051 GP FIFO1
8051 GP FIFO2
8051 GP FIFO3
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001