USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 38

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

Note: This register must be written after PRL for its value to take effect.
Note:
MMU COMMAND Bits 7, 6, and 5 Description:
000
001
010
SMSC DS – USB97C100
NOOP, No operation
Allocate Memory : N3-0 specify how many 128 byte pages to allocate for that packet (up to 10
pages allowed (1280 bytes) per packet.) Immediately generates a "FAILED" code at the ARR
and the code is cleared when complete. Can generate an ALLOC interrupt to MCU upon
completion. When an allocation request cannot be completed due to insufficient memory, the
FAILED bit in the ARR will remain set. Any subsequent release of memory pages (by either
the MMUCR or the SIEDMA) will cause the MMUCR to automatically continue the allocate
command until all requested pages have been successfully allocated. Software should never
issue another allocate command until the previous allocate command has been successfully
completed.
RESET MMU : Frees all buffer RAM, clears interrupts, and resets queue pointers.
[4:3]
[2:0]
[7:4]
[3:0]
[7:5]
[3:0]
BIT
BIT
BIT
This register must be written before writing the “Enqueue Packet into Endpoint x” or the “Reset TX Endpoint
x” command to the MMUCR .
7
6
5
4
AUTO_INCR
MMUTX_SEL
MMU_CMD
Reserved
Reserved
Reserved
(0x7F51)
(0x7F52)
EP[3:0]
A[10:8]
NAME
NAME
(0x7F53)
READ
NAME
MMUCR
N[3:0]
RCV
PRH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Table 62 - Transmit FIFO Select Register
W
W
W
Table 63 - MMU Command Register
Table 61 - Pointer Register (High)
0 = The packet at 0x6000 is the packet pointed to by the PNR
register.
1 = The packet available at 0x6000 is the packet pointed to by the
packet on the top of the RX Packet Number FIFO.
0 = Auto-increment is disabled
1 = Causes the PRH:PRL register to be automatically
incremented each time the 0x6000 data window is accessed.
Data register direction. This bit is required for the MMU/Arbiter to
provide a transparent interface to the buffer RAM for the MCU.
When first set, the MMU immediately fills the read FIFO. The
MCU must wait 2.5us (60 Arbiter clocks) after writing to the
MMU_DATA register before changing this bit from '0' to '1'.
0 = WRITE
1 = READ
Reserved
MSB of the (0-1277 Max) offset of the allocated Packet Pointed to
by PNR. The byte(s) pointed to by this register can be read and
written to by the MCU at 0x6000.
Reserved
This register selects which Endpoint Commands "110" and "111"
will affect when issued to the MMU
MMUCR COMMAND SET
Reserved, writes are ignored and read return “0”
Number of 128 byte Pages. N[3..0]=0000 indicates 1 page, and
N[3..0]=1001 indicates 10 pages, or 1280 bytes.
Page 38
TRANSMIT FIFO SELECT REGISTER
POINTER REGISTER (HIGH)
MMU COMMAND REGISTER
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001