USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 31
USB97C100
Manufacturer Part Number
USB97C100
Description
USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
Manufacturer
Standard Microsystems Corporation
Datasheet
1.USB97C100.pdf
(64 pages)
- Current page: 31 of 64
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Runtime Registers
The DMA controller has a block of 16 R/W registers which normally occupy I/O locations 0x00-0x0F on the ISA bus.
When they are located at 0x0000-0x000F on the ISA bus, the 8051 can access them by programming the IOBASE
Register to 0x00, and reading or writing from 0x4000-0x400F.
SMSC DS – USB97C100
Note: To write to these registers, HLDA must be logic low.
0x000C
0x000D
0x000A
0x000B
0x000E
0x000F
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Table 39 - 8237 Registers in ISA I/O Space
Channel 0: Current Address H/L
Channel 0: Byte Count H/L
Channel 1: Current Address H/L
Channel 1: Byte Count H/L
Channel 2: Current Address H/L
Channel 2: Byte Count H/L
Channel 3: Current Address H/L
Channel 3: Byte Count H/L
Status/Command Register
Write Request Register
Write Single Mask Register
Write Mode Register
Clear Byte Ptr F/F - Read Temp
Register
Master Clear
Clear Mask
Write All Mask Bits
Page 31
Rev. 01/03/2001
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