USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet

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USB97C100

Manufacturer Part Number

USB97C100

Description

USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)

Manufacturer

Standard Microsystems Corporation

Datasheet

1.USB97C100.pdf (64 pages)

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Download datasheet (441Kb)

SMSC DS – USB97C100

High Performance USB Peripheral Controller

Engine

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Complete USB Specification 1.1 Compatibility

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High Speed (12Mbps) Capability

MMU and SRAM Buffer Allow Buffer Optimization

and Maximum Utilization of USB Bandwidth

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Integrated USB Transceiver

Serial Interface Engine (SIE)

8051 Microcontroller (MCU)

Patented Memory Management Unit (MMU)

4 Channel 8237 DMA Controller

(ISADMA)

4K Byte On Board USB Packet Buffer

Quasi-ISA Peripheral Interface

USB Bus Snooping Capabilities

GPIOs

Isochronous, Bulk, Interrupt, and Control

Data Independently Configurable per

Endpoint

Dynamic Hardware Allocation of -Packet

Buffer for Virtual Endpoints

Multiple Virtual Endpoints (up to 16 TX, 16

RX Simultaneously)

Multiple Alternate Address Filters

Dynamic Endpoint Buffer Length

Allocation (0-1280 Byte Packets)

128 Byte Page Size

10 Pages Maximum per Packet

Up to 16 Deep Receive Packet Queue

Up to 5 Deep Transmit Packet Queue, per

Endpoint

Hardware Generated Packet Header

Records Each Packet Status Automatically

Simultaneous Arbitration Between MCU,

SIE, and ISA DMA Accesses

Multi-Endpoint USB Peripheral Controller

Order Number: USB97C100QFP

ORDERING INFORMATION

128 Pin QFP Package

FEATURES

Extended Power Management

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DMA Capability with ISA Memory

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External MCU Memory Interface

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Quasi-ISA Interface Allows Interface to New and

"Legacy" Peripheral Devices

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5V or 3.3v Operation

On Board Crystal Driver Circuit

128 Pin QFP Package

Standard 8051 "Stop Clock" Modes

Additional USB and ISA Suspend

Resume Events

Internal 8MHz Ring Oscillator for Immediate

Low Power Code Execution

24, 16, 12, 8, 4, and 2 MHz PLL Taps For on

the Fly MCU and DMA Clock Switching

Independent Clock/Power Management for

SIE, MMU, DMA and MCU

Four Independent Channels

Transfer Between Internal and External

Memory

Transfer Between I/O and Buffer Memory

External Bus Master Capable

1M Byte Code and Data Storage via 16K

Windows

Flash, SRAM, or EPROM

Downloadable via USB, Serial Port, or ISA

Peripheral

1M ISA Memory Space via 4K MCU Window

64K ISA I/O Space via 256 Byte MCU

Window

4 External Interrupt Inputs

4 DMA Channels

Variable Cycle Timing

8 Bit Data Path

ADVANCE INFORMATION

USB97C100

Rev. 01/03/2001

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