M55800A Atmel Corporation, M55800A Datasheet - Page 96

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

15. AIC: Advanced Interrupt Controller
Figure 15-1. Advanced Interrupt Controller Block Diagram
Note:
96
After a hardware reset, the AIC pins are controlled by the PIO Controller. They must be configured to be controlled by the
peripheral before being used.
AT91M5880A
External Interrupt Sources
Internal Interrupt Sources
Advanced Peripheral
FIQ Source
Bus (APB)
The AT91M55800A has an 8-level priority, individually maskable, vectored interrupt controller.
This feature substantially reduces the software and real-time overhead in handling internal and
external interrupts.
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard
interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be
asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the
interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to
IRQ5.
An 8-level priority encoder allows the customer to define the priority between the different NIRQ
interrupt sources.
Internal sources are programmed to be level sensitive or edge-triggered. External sources can
be programmed to be positive or negative edge-triggered or high- or low-level sensitive.
The interrupt sources are listed in
Table 15-2 on page
Memorization
Memorization
Control
Logic
102.
Table 15-1 on page 97
Prioritization
Controller
Manager
Manager
NFIQ
NIRQ
and the AIC programmable registers in
NIRQ
NFIQ
ARM7TDMI
1745F–ATARM–06-Sep-07
Core