M55800A Atmel Corporation, M55800A Datasheet - Page 225

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.1.1
22.1.2
1745F–ATARM–06-Sep-07
8- or 10-bit Conversion Mode
Trigger Selection
DA = DAVREF x (DAC_DOR / 1024)
When DAC_DOR (Data Output Register) is loaded, the analog output voltage is available after a
settling time of approximately 5 µsec. The exact value depends on the power supply voltage and
the analog output load, and is indicated in the Electrical Characteristics Sheet of the device as
parameter t
The output register cannot be written directly and any data transfer to the DAC must be per-
formed by writing in DAC_DHR (Data Holding Register). The transfer from DAC_DHR to
DAC_DOR is performed automatically or when an hardware trigger occurs, depending on the bit
TRGEN in DAC_MR (Mode Register).
The DAC integrates an output buffer enabling the reduction of the output impedance, and the
possibility of driving external loads directly, without having to add an external operational ampli-
fier. The maximum load supported by the output buffer is indicated in the Electrical
Characteristics of the device.
Bit RES in the Mode Register (DAC_MR) selects between 8-bit or 10-bit modes of operation. In
8-bit mode, the data written in DAC_DHR is automatically shifted left two bits and the two lowest
bits are written 0. The bit RES also affects the type of transfers performed by the PDC channel:
A conversion is triggered when data is written in DAC_DHR and TRGEN in DAC_MR is 0.
If TRGEN is 1, a hardware trigger is selected by the field TTRGSEL between the Timer Counter
Channel outputs TIOA. In this case, the corresponding Timer Counter channel must be pro-
grammed in Waveform Mode, and each time the DAC detects a rising edge on the TC output, it
transfers the last data written in DAC_DHR into DAC_DOR.
The bit DATRDY traces the fact that a valid data has been written in DAC_DHR and not yet
been transferred in DAC_DOR. An interrupt can be generated from this status bit to tell the soft-
ware to load the following value.
• in 8-bit mode, only a byte transfer is performed.
• in 10-bit mode, a half-word transfer (16 bits) is performed.
DAST
.
AT91M5880A
225