M55800A Atmel Corporation, M55800A Datasheet - Page 18

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8. Peripherals
8.1
8.2
8.3
18
Peripheral Registers
Peripheral Interrupt Control
Peripheral Data Controller
AT91M5880A
The AT91M55800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus.
Peripheral registers are only word accessible – byte and half-word accesses are not supported.
If a byte or a half-word access is attempted, the memory controller automatically masks the low-
est address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address
space).
The following registers are common to all peripherals:
Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward
compatibility. These bits read 0.
The Interrupt Control of each peripheral is controlled from the status register using the interrupt
mask. The status register bits are ANDed to their corresponding interrupt mask bits and the
result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt
Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes
it possible to enable or disable peripheral interrupt sources with a non-interruptible single
instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-time
and multi-tasking systems.
An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the on-chip
USARTs/SPI and the on and off-chip memories without processor intervention. One PDC chan-
nel is connected to the receiving channel and one to the transmitting channel of each USART
and SPI.
The user interface of a PDC channel is integrated in the memory space of each peripheral. It
contains a 32-bit address pointer register and a 16-bit count register. When the programmed
data is transferred, an end of transfer interrupt is generated by the corresponding peripheral.
• Control Register – Write-only register that triggers a command when a one is written to the
• Mode Register – read/write register that defines the configuration of the peripheral. Usually
• Data Register – read and/or write register that enables the exchange of data between the
• Status Register – Read-only register that returns the status of the peripheral.
• Enable/Disable/Status Registers – shadow command registers. Writing a one in the Enable
corresponding position at the appropriate address. Writing a zero has no effect.
has a value of 0x0 after a reset.
processor and the peripheral.
Register sets the corresponding bit in the Status Register. Writing a one in the Disable
Register resets the corresponding bit and the result can be read in the Status Register.
Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit
manipulation, and enables modification of a register with a single non-interruptible
instruction, replacing the costly read-modify-write operation.
1745F–ATARM–06-Sep-07