M55800A Atmel Corporation, M55800A Datasheet - Page 210

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

20.7.13
Register Name:
Access Type:
Reset State:
Offset:
• CPOL: Clock Polarity (Code Label SP_CPOL)
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce a desired
clock/data relationship between master and slave devices.
• NCPHA: Clock Phase (Code Label SP_NCPHA)
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce a desired clock/data relationship between master and slave devices.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
210
31
23
15
7
AT91M5880A
SPI Chip Select Register
BITS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SP_CSR0.. SP_CSR3
Read/Write
0
0x30......0x3C
30
22
14
6
BITS
29
21
13
5
Bits Per Transfer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10
11
12
13
14
15
16
28
20
12
4
8
9
DLYBCT
DLYBS
SCBR
27
19
11
–
3
26
18
10
2
–
Code Label: SP_BITS
SP_BITS_10
SP_BITS_11
SP_BITS_12
SP_BITS_13
SP_BITS_14
SP_BITS_15
SP_BITS_16
SP_BITS_8
SP_BITS_9
NCPHA
25
17
9
1
–
–
–
–
–
–
–
1745F–ATARM–06-Sep-07
CPOL
24
16
8
0