M55800A Atmel Corporation, M55800A Datasheet
M55800A
Specifications of M55800A
Related parts for M55800A
M55800A Summary of contents
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... Available in a 176-lead LQFP (Green) and a 176-ball BGAPackage (RoHS-compliant) 1. Description The AT91M55800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption ...
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... The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip SRAM, a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip, the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many ultra low-power applications. ...
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... AD7 169 (1) ADVREF 170 (1) DAVREF 171 (1) DA0 172 (1) DA1 173 (1) GNDA 174 VDDCORE 175 VDDIO 176 AT91M55800A GND GND NCS4 NCS5 NCS6 NCS7 PB0 PB1 PB2 PB3/IRQ4 PB4/IRQ5 PB5 PB6/AD0TRIG PB7/AD1TRIG VDDIO GND PB8 PB9 PB10 PB11 PB12 PB13 PB14 ...
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... F5 D6 JTAGSEL F6 D7 GND F7 D8 PB15 F8 D9 PB14 F9 PB5 F10 PB1 F11 GND F12 VDDCORE F13 AD7 F14 VDDA F15 AT91M55800A Pin AT91M55800A GND G4 – G5 – G6 – G7 – G8 – G9 – G10 – G11 AD6 G12 AD5 G13 NRSTBU ...
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... PB27/TIOB2 P8 M9 PA0/TCLK3 P9 M10 GND P10 M11 PA23/SPCK P11 M12 GND P12 M13 PA21/TXD2 P13 M14 PA24/MISO P14 M15 XIN P15 AT91M5880A AT91M55800A Pin AT91M55800A VDDIO R3 D14 R4 PB19/TCLK0 R5 VDDIO R6 PB25/TCLK2 R7 PA1/TIOA3 R8 VDDIO R9 PA8/TIOB5 R10 PA9/IRQ0 R11 VDDCORE R12 VDDIO ...
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Figure 2-1. Figure 2-2. AT91M5880A 6 176-lead LQFP Pinout 132 133 176 1 176-ball BGA Pinout ...
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Pin Description Table 3-1. Pin Description Module Name A0 - A23 D0 - D15 NCS0 - NCS7 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT BMS IRQ0 - IRQ5 AIC FIQ TCLK0 - TCLK5 Timer TIOA0 - TIOA5 ...
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Table 3-1. Pin Description (Continued) Module Name Function DA0 - DA1 Analog output channels DAC DAVREF Analog reference XIN Main oscillator input XOUT Main oscillator output PLLRC RC filter for PLL Clock XIN32 32 kHz oscillator input ...
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Block Diagram Figure 4-1. Block Diagram JTAGSEL NTRST TMS TDO TDI TCK PB0 PB1 PB2 PB5 PB8 P PB9 I PB10 PB11 O PB12 B PB13 PB14 PB15 PB16 PB17 PB3/IRQ4 PB4/IRQ5 PA9/IRQ0 PA10/IRQ1 PA11/IRQ2 PA12/IRQ3 PA13/FIQ PA14/SCK0 PA15/TXD0 ...
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... Memory The AT91M55800A microcontroller embeds 8K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. The AT91M55800A microcontroller features an External Bus Interface (EBI), which enables con- nection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device ...
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The Real-time Clock (RTC) peripheral is designed for very low power consumption, and com- bines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar, complemented by a programmable periodic interrupt. The Parallel Input/Output Controllers (PIOA and PIOB) ...
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... Power consumption Thermal and reliability considerations AC characteristics Product overview Ordering information Packaging information Soldering profile AT91M5880A 12 Document Title ARM7TDMI (Thumb) Datasheet AT91M55800A Datasheet (This document) AT91M55800A Electrical Characteristics AT91M55800A Summary Datasheet Literature Number 0673 1745 1727 1745S 1745F–ATARM–06-Sep-07 ...
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... Input/Output Considerations After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility recommended that in any application phase, the inputs to the AT91M55800A microcontroller be held at valid logic levels to minimize the power consumption. 1745F–ATARM–06-Sep-07 Nominal Power Combinations ...
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... JTAGSEL pin after the last valid NRST. In either Boundary Scan or ICE Mode a reset can be performed from the same or different cir- cuitry, as shown in asserted after each power-up. (See the AT91M55800A electrical datasheet, Atmel lit° 1727, for the necessary minimum pulse assertion time.) Figure 7-1. Notes: ...
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... The AT91M55800A provides a Tri-state Mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In Tri-state Mode, all the output pin drivers of the AT91M55800A microcontroller are disabled. ...
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... The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91M55800A microcontroller uses a remap command that enables switching between the boot memory and the internal RAM bank addresses ...
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External Bus Interface The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0 0000. It generates the signals that control access to the external devices, and can configure up to eight 16-Mbyte banks. In all cases ...
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... Peripherals The AT91M55800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible – byte and half-word accesses are not supported byte or a half-word access is attempted, the memory controller automatically masks the low- est address bits and generates a word access. ...
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... Power down: RTC active, supply on the rest of the circuit deactivated 8.4.2 RTC: Real-time Clock The AT91M55800A features a Real-time Clock (RTC) peripheral that is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar, complemented by a programmable periodic interrupt. ...
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... TC: Timer Counter The AT91M55800A features two Timer Counter blocks that include three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse gen- eration, delay timing and pulse-width modulation. ...
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Each channel can be enabled or disabled independently, and has its own data register. The ADC can be configured to automatically enter Sleep mode after a conversion sequence, and can be triggered by the software, the Timer Counter ...
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... Memory Map Figure 9-1. AT91M55800A Memory Map Before and after Remap Command Before Remap Address Function Size 0xFFFFFFFF On-chip 4M Bytes Peripherals 0xFFC00000 0xFFBFFFFF Reserved 0x00400000 0x003FFFFF On-chip RAM 1M Byte 0x00300000 0x002FFFFF Reserved 1M Byte On-chip Device 0x00200000 0x001FFFFF Reserved 1M Byte On-chip Device 0x00100000 ...
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... Peripheral Memory Map Figure 1. AT91M55800A Peripheral Memory Map 1745F–ATARM–06-Sep-07 Address Peripheral Peripheral Name 0xFFFFFFFF AIC Advanced Interrupt Controller 0xFFFFF000 Reserved 0xFFFFBFFF WD WatchdogTimer 0xFFFF8000 0xFFFF7FFF APMC Advanced Power Management Controller 0xFFFF4000 0xFFFF3FFF PIO B Parallel I/O Controller B 0xFFFF0000 0xFFFEFFFF Parallel I/O Controller A ...
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EBI: External Bus Interface The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully-programmable and can address up to 128M bytes. It has eight chip selects and a 24-bit ...
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External Memory Mapping The memory map associates the internal 32-bit address space with the external 24-bit address bus. The memory map is defined by programming the base address and page size of the external memories (see EBI User Interface ...
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EBI Pin Description Name A0 - A23 D0 - D15 NCS0 - NCS7 NRD NWR0 - NWR1 NOE NWE NUB, NLB NWAIT The following table shows how certain EBI signals are multiplexed: Multiplexed Signals A0 NRD NWR0 NWR1 AT91M5880A ...
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Data Bus Width A data bus width bits can be selected for each chip select. This option is controlled by the DBW field in the EBI_CSR (Chip-select Register) for the corresponding chip select. Figure 11-2 ...
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Figure 11-4. Memory Connection for 2 x 8-bit Data Busses Byte-select Access is used to connect 16-bit devices in a memory page. • The signal A0/NLB is used as NLB and enables the lower byte for both read and write ...
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Figure 11-6 Figure 11-6. Connection for a 16-bit Data Bus Without Byte-write Capability. 11.5 Boot on NCS0 Depending on the device and the BMS pin level during the reset, the user can select either an 8- bit or 16-bit external ...
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Read Protocols The EBI provides two alternative protocols for external memory read access: standard and early read. The difference between the two protocols lies in the timing of the NRD (read cycle) waveform. The protocol is selected by the ...
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Figure 11-8. Early Read Protocol 11.6.3 Early Read Wait State In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle ...
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Write Data Hold Time During write cycles in both protocols, output data becomes valid after the falling edge of the NWE signal and remains valid after the rising edge of NWE, as illustrated in the figure below. The external ...
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Wait States The EBI can automatically insert wait states. The different types of wait states are listed below: • Standard wait states • Data float wait states • External wait states • Chip select change wait states • Early ...
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Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t memory. The EBI keeps track of the programmed external data float time during internal accesses, to ensure that the ...
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Figure 11-13. External Wait Notes: 11.8.4 Chip Select Change Wait States A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no wait states have already been inserted). If any wait ...
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Memory Access Waveforms Figure 11-15 memory read access. Figure 11-15. Standard Read Protocol with no t AT91M5880A 36 through Figure 11-18 show examples of the two alternative protocols for external DF 1745F–ATARM–06-Sep-07 ...
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Figure 11-16. Early Read Protocol with no t 1745F–ATARM–06-Sep-07 AT91M5880A DF 37 ...
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Figure 11-17. Standard Read Protocol with t AT91M5880A 38 DF 1745F–ATARM–06-Sep-07 ...
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Figure 11-18. Early Read Protocol with t 1745F–ATARM–06-Sep-07 AT91M5880A DF 39 ...
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... Figure 11-19 access to the various AT91M55800A external memory devices. The configurations described are as follows: Table 11-1. Figure Number 11-19 11-20 11-21 11-22 11-23 11-24 11-25 AT91M5880A 40 through Figure 11-25 show the timing cycles and wait states for read and write Memory Access Waveforms Number of Wait States Bus Width ...
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Figure 11-19. 0 Wait States, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ ...
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Figure 11-20. 1 Wait State, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ ...
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Figure 11-21. 1 Wait State, 16-bit Bus Width, Half-word Transfer A1 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus · Early Protocol D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - ...
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Figure 11-22. 0 Wait States, 8-bit Bus Width, Word Transfer MCK ADDR A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - ...
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Figure 11-23. 1 Wait State, 8-bit Bus Width, Half-word Transfer 1 Wait State MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 ...
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Figure 11-24. 1 Wait State, 8-bit Bus Width, Byte Transfer MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0-D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0-D15 AT91M5880A 46 1 Wait ...
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Figure 11-25. 0 Wait States, 16-bit Bus Width, Byte Transfer MCK A1-A23 Internal Address NCS NLB NUB READ ACCESS · Standard Protocol NRD D0-D15 Internal Bus · Early Protocol NRD D0-D15 WRITE ACCESS · Byte Write Option NWR0 NWR1 D0-D15 ...
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EBI User Interface The EBI is programmed using the registers listed in the table below. The Remap Control Regis- ter (EBI_RCR) controls exit from Boot Mode (see Memory Control Register (EBI_MCR) is used to program the number of active ...
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EBI Chip Select Register Register Name: EBI_CSR0 - EBI_CSR7 Access Type: Read/Write Reset Value: See Table 11-2 Absolute Address: 0xFFE00000 - 0xFFE0001C – – PAGES – • DBW: Data Bus ...
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PAGES: Page Size PAGES Page Size 16M Bytes 1 1 64M Bytes • TDF: Data Float Output Time TDF ...
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EBI Remap Control Register Register Name: EBI_RCR Access Type: Write-only Absolute Address: 0xFFE00020 Offset: 0x20 31 30 – – – – – – – – • RCB: Remap Command Bit (Code Label EBI_RCB) ...
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... Main Power is used throughout this document to identify the voltages powering the AT91M55800A and other components of the system, with the exception of the Battery Backup voltage, which is applied to the VDDBU. Main Power supplies VDDIO, VDDCORE and, if required, the analog voltage VDDA. A battery or battery capacitor generally supplies the Battery Backup Power ...
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Operating Modes Five operating modes are supported by the APMC and offer different power consumption levels and event response latency times. • Normal Mode: The Main Power supply is switched on; the ARM Core Clock is enabled and the ...
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Figure 12-2. APMC Block Diagram WKEDG WAKEUP Edge Detector NRSTBU XIN32 XOUT32 MOSCEN XIN Main Oscillator XOUT MOSCBYP APMC_SCDR Set IDLE MODE FF Clear NIRQ NFIQ Note: 1. The RTC is described in another chapter AT91M5880A 54 WKACKC ALWKEN ALSHEN ...
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... Slow Clock Generator The AT91M55800A has a very low power 32 kHz oscillator powered by the backup battery volt- age supplied on the VDDBU pins. The XIN32 and XOUT32 pins must be connected to a 32768 Hz crystal. The oscillator has been especially designed to connect typical load capaci- tance crystal and does not require any external capacitor integrates the XIN32 and XOUT32 capacitors to ground ...
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Clock Generator The clock generator consists of the main oscillator, the PLL and the clock selection logic with its prescaler. It aims at selecting the Master Clock, called MCK throughout this datasheet. The clock generator also contains the circuitry ...
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Note: If the PLL multiplication is changed while the PLL is already active, the LOCK bit in APMC_SR is automatically cleared and the same sequence is restarted. The PLL is automatically bypassed while the frequency is changing (while LOCK is ...
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Figure 12-6. Clock Switch 12.3.5 Slow Clock Interrupt The APMC also features the Slow Clock interrupt, allowing the user to detect when the Master Clock is actually switched to the Slow Clock. Switching from the Slow Clock to a higher ...
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... System Clock The AT91M55800A has only one system clock: the ARM Core clock. It can be enabled and dis- abled by writing to the System Clock Enable (APMC_SCER) and System Clock Disable Registers (APMC_SCDR). The status of the ARM Core clock (at least for debug purposes) can be read in the System Clock Status Register (APMC_SCSR) ...
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Figure 12-7. Shut-down and Wake-up Features Power DC/DC Converter Supply SHD Resistor required by some DC/DC Converters To accommodate the different types of main power supply available, and different signals that can command the shut-down of this device, tri-state, level ...
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First Start-up Sequence At initial startup, or after VDDBU has been disconnected, the battery-supplied logic must be initialized. The Battery Backup Reset sets the following default state: • Shut-down Logic Initialized in the Wake-up state (or Non Alarm) • ...
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APMC User Interface Base Address:0xFFFF4000 (Code Label APMC_BASE) Table 12-1. Register Mapping Offset Register 0x00 System Clock Enable Register 0x04 System Clock Disable Register 0x08 System Clock Status Register 0x0C Reserved 0x10 Peripheral Clock Enable Register 0x14 Peripheral Clock ...
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APMC System Clock Enable Register Register Name: APMC_SCER Access Type: Write-only Offset: 0x00 31 30 – – – – – – – – • CPU: System Clock Enable Bit effect. ...
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APMC System Clock Status Register Register Name: APMC_SCSR Access Type: Read-only Reset Value: 0x1 Offset: 0x08 31 30 – – – – – – – – • CPU: System Clock Status Bit 0 ...
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APMC Peripheral Clock Disable Register Register Name: APMC_PCDR Access Type: Write-only Offset: 0x14 31 30 – – – – ADC0 PIOB 7 6 TC1 TC0 • Peripheral Clock Disable (per peripheral effect. ...
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APMC Clock Generator Mode Register Register Name: APMC_CGMR Access Type: Read/Write Reset Value: 0x0 Offset: 0x20 31 30 – – CSS 7 6 – • MOSCBYP: Main Oscillator Bypass (Code Label APMC_MOSC_BYP Crystal ...
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MUL: Phase Lock Loop Factor 0 = The PLL is deactivated, reducing power consumption to a minimum The PLL output higher frequency (MUL+1) than the input if the bit lock is set ...
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APMC Power Control Register Register Name: APMC_PCR Access Type: Write-only Offset: 0x28 31 30 – – – – – – – – • SHDALC: Shut-down or Alarm Command (Code Label APMC_SHDALC ...
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APMC Power Mode Register Register Name: APMC_PMR Access Type: Read/Write Backup Reset Value:0x1 Offset: 0x2C 31 30 – – – – – – WKEDG • SHDALS: Shut-down or Alarm Output Selection This field ...
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WKEDG: Wake-up Input Edge Selection This field defines the edge to detect on the Wake-up pin (WAKEUP) to provoke a wake-up. WKEDG Wake-up Input Edge Selection 0 0 None. No edge is detected on wake-up Positive edge ...
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APMC Status Register Register Name: APMC_SR Access Type: Read-only Offset: 0x30 31 30 – – – – – – – – • MOSCS: Main Oscillator Status (Code Label APMC_MOSCS Main Oscillator ...
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APMC Interrupt Enable Register Register Name: APMC_IER Access Type: Write-only Offset: 0x34 31 30 – – – – – – – – • MOSCS: Main Oscillator Interrupt Enable (Code Label APMC_MOSCS ...
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APMC Interrupt Mask Register Register Name: APMC_IMR Access Type: Read-only Reset Value: 0x0 Offset: 0x3C 31 30 – – – – – – – – • MOSCS: Main Oscillator Interrupt Mask (Code Label ...
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... RTC: Real-time Clock The AT91M55800A features a Real-time Clock (RTC) peripheral that is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar, complemented by a programmable periodic interrupt. The time and calendar values are coded in Binary-Coded Decimal (BCD) format. The time for- mat can be 24-hour mode or 12-hour mode with an AM/PM indicator ...
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Functional Description The RTC provides a full Binary-Coded Decimal (BCD) clock which includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099, a two-hundred year Gregorian calendar ...
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Hour (BCD check, in 24-hour mode check range and check that AM/PM flag is not set if RTC is set in 24-Hour mode, in 12-Hour mode check range 01 - 12) 7. Minute (check BCD and ...
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RTC User Interface Base Address:0xFFFB8000 (Code Label RTC_BASE) Table 13-1. Register Mapping Offset Register 0x0000 Mode Register 0x0004 Hour Mode Register 0x0008 Time Register 0x000C Calendar Register 0x0010 Time Alarm Register 0x0014 Calendar Alarm Register 0x0018 Status Register 0x001C ...
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RTC Mode Register Register Name: RTC_MR Access: Read/Write Offset: 0x00 31 30 – – – – – – – – • UPDTIM: Update Request Time Register (Code Label RTC_UPDTIM Enables the ...
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RTC Hour Mode Register Register Name: RTC_HMR Access Type: Read/Write Reset State: 0x0 Offset: 0x04 31 30 – – – – – – – – • HRMOD: 12/24 Hour Mode HRMOD Selected HRMOD ...
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RTC Time Register Register Name: RTC_TIMR Access Type: Read/Write Reset State: 0x0 Offset: 0x08 31 30 – – – AMPM 15 14 – – • SEC: Current Second (Code Label RTC_SEC) The range that can ...
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RTC Calendar Register Register Name: RTC_CALR Access Type: Read/Write Reset State: 0x01819819 Offset: 0x0C 31 30 – – DAY – – • CENT: Current Century (Code Label RTC_CENT) The range that can be ...
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RTC Time Alarm Register Register Name: RTC_TAR Access Type: Read/Write Reset State: 0x0 Offset: 0x10 31 30 – – HOUREN AMPM 15 14 MINEN 7 6 SECEN • SEC: Second Alarm This field is the alarm field ...
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RTC Calendar Alarm Register Register Name: RTC_CAR Access Type: Read/Write Reset State: 0x0 Offset: 0x14 31 30 – DATEN 23 22 – MTHEN 15 14 – – – – • MONTH: Month Alarm This field is the ...
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RTC Status Register Register Name: RTC_SR Access Type: Read-only Reset State: 0x0 Offset: 0x18 31 30 – – – – – – – – • ACKUPD: Acknowledge for Update (Code Label RTC_ACKUPD) 0 ...
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RTC Status Clear Register Register Name: RTC_SCR Access Type: Write-only Offset: 0x1C 31 30 – – – – – – – – • ACKUPD: Acknowledge for Update Interrupt Clear (Code Label RTC_ACKUPD) 0 ...
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RTC Interrupt Enable Register Register Name: RTC_IER Access Type: Write-only Offset: 0x20 31 30 – – – – – – – – • ACKUPD: Acknowledge Update Interrupt Enable (Code Label RTC_ACKUPD ...
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RTC Interrupt Disable Register Register Name: RTC_IDR Access Type: Write-only Offset: 0x24 31 30 – – – – – – – – • ACKUPD: Acknowledge Update Interrupt Disable (Code Label RTC_ACKUPD ...
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RTC Interrupt Mask Register Register Name: RTC_IMR Access Type: Read-only Reset State: 0x0 Offset: 0x28 31 30 – – – – – – – – • ACKUPD: Acknowledge Update Interrupt Mask (Code Label ...
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RTC Valid Entry Register Register Name: RTC_VER Access Type: Read-only Reset State: 0x0 Offset: 0x2C 31 30 – – – – – – – – • NVT: Non-Valid Time (Code Label RTC_NVT) 0 ...
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... WD: Watchdog Timer The AT91M55800A has an internal Watchdog Timer that can be used to prevent system lock-up if the software becomes trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer overflow occurs overflow does occur, the watchdog timer generates one or a combination of the fol- lowing signals, depending on the parameters in WD_OMR (Overflow Mode Register): • ...
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WD User Interface WD Base Address: 0xFFFF8000 (Code Label WD_BASE) Table 14-1. Register Mapping Offset Register 0x00 Overflow Mode Register 0x04 Clock Mode Register 0x08 Control Register 0x0C Status Register 1745F–ATARM–06-Sep-07 AT91M5880A Name Access WD_OMR Read/Write WD_CMR Read/Write WD_CR ...
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WD Overflow Mode Register Name: WD_OMR Access: Read/Write Reset Value: 0 Offset: 0x00 31 30 – – – – OKEY • WDEN: Watchdog Enable (Code Label WD_WDEN Watchdog is disabled and ...
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WD Clock Mode Register Name: WD_CMR Access: Read/Write Reset Value: 0 Offset: 0x04 31 30 – – – – – CKEY • WDCLKS: Clock Selection WDCLKS Clock Selected 0 0 MCK/ ...
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WD Control Register Name: WD_CR Access: Write-only Offset: 0x08 31 30 – – – – • RSTKEY: Restart Key (Code Label WD_RSTKEY) 0xC071 = Watch Dog counter is restarted. Other value = No ...
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WD Status Register Name: WD_SR Access: Read-only Reset Value: 0x0 Offset: 0x0C 31 30 – – – – – – – – • WDOVF: Watchdog Overflow (Code Label WD_WDOVF watchdog ...
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... AIC: Advanced Interrupt Controller The AT91M55800A has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’ ...
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Table 15-1. AIC Interrupt Sources Interrupt Source Interrupt Name ...
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Hardware Interrupt Vectoring The hardware interrupt vectoring reduces the number of instructions to reach the interrupt han- dler to only one. By storing the following instruction at address 0x00000018, the processor loads the program counter with the interrupt handler ...
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Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR. The interrupt mask can be read in the Read-only register AIC_IMR. A disabled interrupt does not affect the servicing of ...
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The same mechanism of Spurious Interrupt occurs if the ARM7TDMI reads the IVR (application software or ICE) when there is no interrupt pending. This mechanism is also valid for the FIQ interrupts. Once the AIC enters the Spurious Interrupt management, ...
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The following table shows the main steps of an interrupt and the order in which they are per- formed according to the mode: Action Calculate active interrupt (higher than current or spurious) Determine and return the vector of the active ...
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AIC User Interface Base Address: 0xFFFFF000 (Code Label AIC_BASE) Table 15-2. Register Mapping Offset Register 0x000 Source Mode Register 0 0x004 Source Mode Register 1 – – 0x07C Source Mode Register 31 0x080 Source Vector Register 0 0x084 Source ...
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AIC Source Mode Register Register Name: AIC_SMR0...AIC_SMR31 Access Type: Read/Write Reset Value – – – – – – – SRCTYPE • PRIOR: Priority Level (Code Label AIC_PRIOR) Program the priority ...
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AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Read/Write Reset Value • VECTOR: Interrupt Handler Address The user may store in these registers the addresses of the corresponding handler ...
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AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read-only Reset Value: 0 Offset: 0x104 • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user ...
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AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Read-only Reset Value: Undefined Offset: 0x10C 31 30 COMMRX COMMTX 23 22 – SLCKIRQ 15 14 ADC0IRQ PIOBIRQ 7 6 TC1IRQ TC0IRQ • Interrupt Pending 0 = Corresponding interrupt is ...
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AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only Reset Value: 0 Offset: 0x114 31 30 – – – – – – – – • NFIQ: NFIQ Status (Code Label AIC_NFIQ) ...
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AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write-only Offset: 0x124 31 30 COMMRX COMMTX 23 22 – SLCKIRQ 15 14 ADC0IRQ PIOBIRQ 7 6 TC1IRQ TC0IRQ • Interrupt Disable effect Disables ...
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AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only Offset: 0x12C 31 30 COMMRX COMMTX 23 22 SLCKIRQ – ADC0IRQ PIOBIRQ 7 6 TC1IRQ TC0IRQ • Interrupt Set effect Sets ...
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AIC Spurious Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: 0 Offset: 0x134 • SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the Spurious ...
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Standard Interrupt Sequence It is assumed that: • The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded with corresponding interrupt service routine addresses and interrupts are enabled. • The Instruction at address 0x18(IRQ exception vector address) is ldr ...
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Note: AT91M5880A 112 The I bit in the SPSR is significant set, it indicates that the ARM Core was just about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, ...
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... PIO: Parallel I/O Controller The AT91M55800A has 58 programmable I/O lines. 13 pins are dedicated as general-purpose I/O pins. The other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB. The PIO controller enables the generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins ...
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I/O line. The register PIO_IFSR (Input Filter Status) indicates whether or not the filter is activated for each pin. 16.5 Interrupts Each parallel I/O can be ...
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Figure 16-1. Parallel I/O Multiplexed with a Bi-directional Signal Pad Output Enable Pad Output Pad Pad Input Note: 1. See “Section 16.8 ”PIO Connection Tables” 1745F–ATARM–06-Sep- PIO_PSR PIO_MDSR Filter 1 0 OFF (1) Value PIO_IFSR PIO_PSR PIO_PDSR Event ...
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PIO Connection Tables Table 16-1. PIO Controller A Connection Table PIO Controller Bit Port Number Name Port Name 0 PA0 TCLK3 1 PA1 TIOA3 2 PA2 TIOB3 3 PA3 TCLK4 4 PA4 TIOA4 5 PA5 TIOB4 6 PA6 TCLK5 ...
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Table 16-2. PIO Controller B Connection Table PIO Controller Bit Port Number Name Port Name 0 PB0 – 1 PB1 – 2 PB2 – 3 PB3 IRQ4 4 PB4 IRQ5 5 PB5 – 6 PB6 AD0TRIG 7 PB7 AD1TRIG 8 ...
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PIO User Interface PIO Controller A Base Address:0xFFFEC000 (Code Label PIOA_BASE) PIO Controller B Base Address:0xFFFF0000 (Code Label PIOB_BASE) Table 16-3. Register Mapping Offset Register 0x00 PIO Enable Register 0x04 PIO Disable Register 0x08 PIO Status Register 0x0C Reserved ...
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PIO Enable Register Register Name: PIO_PER Access Type: Write-only Offset: 0x00 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to enable individual pins to be controlled by ...
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PIO Status Register Register Name: PIO_PSR Access Type: Read-only Offset: 0x08 Reset Value: 0x3FFFFFFF (A) 0x0FFFFFFF ( P31 P30 23 22 P23 P22 15 14 P15 P14 This register indicates which pins are ...
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PIO Output Disable Register Register Name: PIO_ODR Access Type: Write-only Offset: 0x14 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to disable PIO output drivers. If the ...
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PIO Input Filter Enable Register Register Name: PIO_IFER Access Type: Write-only Offset: 0x20 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to enable input glitch filters. It ...
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PIO Input Filter Status Register Register Name: PIO_IFSR Access Type: Read-only Offset: 0x28 Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 This register indicates which pins have glitch ...
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PIO Clear Output Data Register Register Name: PIO_CODR Access Type: Write-only Offset: 0x34 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to clear PIO output data. It ...
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PIO Pin Data Status Register Register Name: PIO_PDSR Access Type: Read-only Offset: 0x3C Reset Value: Undefined 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register shows the state of the ...
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PIO Interrupt Disable Register Register Name: PIO_IDR Access Type: Write-only Offset: 0x44 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to disable PIO interrupts on the corresponding ...
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PIO Interrupt Status Register Register Name: PIO_ISR Access Type: Read-only Offset: 0x4C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 This register indicates for each pin when a ...
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PIO Multi-driver Disable Register Register Name: PIO_MDDR Access Type: Write-only Offset: 0x54 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to disable the open drain configuration of ...
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... SF: Special Function Registers The AT91M55800A provides registers which implement the following special functions. • Chip identification • RESET status 17.1 Chip Identifier The following chip identifier values are covered in this datasheet: Product AT91M55800A 17.2 SF User Interface Chip ID Base Address = 0xFFF00000 (Code Label SF_BASE) Table 17-1 ...
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Chip ID Register Register Name: SF_CIDR Access Type: Read-only Offset: 0x00 31 30 EXT 23 22 ARCH 15 14 NVDSIZ • VERSION: Version of the chip (Code Label SF_VERSION) This value is incremented by one ...
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ARCH: Chip Architecture Code of Architecture: Two BCD digits ARCH 0110 0011 0100 0000 0101 0101 • NVPTYP: Nonvolatile Program Memory Type NVPTYP Note: All other codes are reserved. • EXT: Extension Flag ...
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Reset Status Register Register Name: SF_RSR Access Type: Read-only Offset: 0x08 31 30 – – – – – – • RESET: Reset Status Information This field indicates whether the reset was demanded by ...
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SF Protect Mode Register Register Name: SF_PMR Access Type: Read/Write Reset Value: 0x0 Offset: 0x18 – – – – • PMRKEY: Protect Mode Register Key Used only when writing SF_PMR. PMRKEY ...
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... USART: Universal Synchronous/ Asynchronous Receiver/Transmitter The AT91M55800AA provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters which are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator • Parity, Framing and Overrun Error Detection • Line Break Generation and Detection • ...
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Pin Description Table 18-1. USART Channel External Signals Name Description USART Serial clock can be configured as input or output: SCK SCK is configured as input if an External clock is selected (USCLKS[ SCK is driven as ...
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Baud Rate Generator The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the Receiver and the Transmitter. The Baud Rate Generator can select between external and internal clock sources. The external clock source ...
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Receiver 18.3.1 Asynchronous Receiver The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of US_MR). In asynchronous mode, the USART detects the start of a received character by sampling the RXD signal until it detects ...
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Synchronous Receiver When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate clock low level is detected considered as a start. Data bits, ...
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Transmitter The transmitter has the same behavior in both synchronous and asynchronous operating modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock. See ...
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Break A break condition is a low signal level which has a duration of at least one character (including start/stop bits and parity). 18.6.1 Transmit Break The transmitter generates a break condition on the TXD line when STTBRK is ...
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The standard break transmission sequence is: 1. Wait for the transmitter ready (US_CSR.TXRDY = 1) 2. Send the STTBRK command (write 0x0200 to US_CR) 3. Wait for the transmitter ready (bit TXRDY = 1 in US_CSR) 4. Send the STPBRK ...
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Peripheral Data Controller Each USART channel is closely connected to a corresponding Peripheral Data Controller chan- nel. One is dedicated to the receiver. The other is dedicated to the transmitter. Note: The PDC channel is programmed using US_TPR (Transmit ...
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Figure 18-7. Channel Modes 1745F–ATARM–06-Sep-07 Automatic Echo Receiver Disabled Transmitter Local Loopback Disabled Receiver Disabled Transmitter Remote Loopback V DD Disabled Receiver Disabled Transmitter AT91M5880A RXD TXD RXD V DD TXD RXD TXD 143 ...
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USART User Interface Base Address USART0: 0xFFFC0000 (Code Label USART0_BASE) Base Address USART1: 0xFFFC4000 (Code Label USART1_BASE) Base Address USART2: 0xFFFC8000 (Code Label USART2_BASE) Table 18-2. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Interrupt Enable ...
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USART Control Register Name: US_CR Access Type: Write-only Offset: 0x00 31 30 – – – – – – TXDIS TXEN • RSTRX: Reset Receiver (Code Label US_RSTRX effect ...
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STTBRK: Start Break (Code Label US_STTBRK effect break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. • STPBRK: ...
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USART Mode Register Name: US_MR Access Type: Read/Write Reset State: 0 Offset: 0x04 31 30 – – – – CHMODE 7 6 CHRL • USCLKS: Clock Selection (Baud Rate Generator Input Clock) USCLKS 0 0 ...
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NBSTOP: Number of Stop Bits The interpretation of the number of stop bits depends on SYNC. NBSTOP Asynchronous (SYNC = stop bit 0 1 1.5 stop bits stop bits 1 1 Reserved ...
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USART Interrupt Enable Register Name: US_IER Access Type: Write-only Offset: 0x08 31 30 – – – – – – PARE FRAME • RXRDY: Enable RXRDY Interrupt (Code Label US_RXRDY effect. ...
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TIMEOUT: Enable Time-out Interrupt (Code Label US_TIMEOUT effect Enables Reception Time-out Interrupt. • TXEMPTY: Enable TXEMPTY Interrupt (Code Label US_TXEMPTY effect Enables TXEMPTY Interrupt. AT91M5880A 150 1745F–ATARM–06-Sep-07 ...
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USART Interrupt Disable Register Name: US_IDR Access Type: Write-only Offset: 0x0C 31 30 – – – – – – PARE FRAME • RXRDY: Disable RXRDY Interrupt (Code Label US_RXRDY effect. ...
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TIMEOUT: Disable Time-out Interrupt (Code Label US_TIMEOUT effect Disables Receiver Time-out Interrupt. • TXEMPTY: Disable TXEMPTY Interrupt (Code Label US_TXEMPTY effect Disables TXEMPTY Interrupt. AT91M5880A 152 1745F–ATARM–06-Sep-07 ...
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USART Interrupt Mask Register Name: US_IMR Access Type: Read-only Reset Value: 0x0 Offset: 0x10 31 30 – – – – – – PARE FRAME • RXRDY: RXRDY Interrupt Mask (Code Label US_RXRDY) 0 ...
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TIMEOUT: Time-out Interrupt Mask (Code Label US_TIMEOUT Receive Time-out Interrupt is Disabled Receive Time-out Interrupt is Enabled. • TXEMPTY: TXEMPTY Interrupt Mask (Code Label US_TXEMPTY TXEMPTY Interrupt is Disabled TXEMPTY Interrupt ...
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USART Channel Status Register Name: US_CSR Access Type: Read-only Reset: 0x18 Offset: 0x14 31 30 – – – – – – PARE FRAME • RXRDY: Receiver Ready (Code Label US_RXRDY ...
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PARE: Parity Error (Code Label US_PARE least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last “Reset Status Bits” command parity bit has been ...
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USART Receiver Holding Register Name: US_RHR Access Type: Read-only Reset State: 0 Offset: 0x18 31 30 – – – – – – • RXCHR: Received Character Last character received if RXRDY is set. ...
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USART Baud Rate Generator Register Name: US_BRGR Access Type: Read/Write Reset State: 0 Offset: 0x20 31 30 – – – – • CD: Clock Divisor This register has no effect if Synchronous Mode ...
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USART Receiver Time-out Register Name: US_RTOR Access Type: Read/Write Reset State: 0 Offset: 0x24 31 30 – – – – – – • TO: Time-out Value When a value is written to this ...
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USART Receive Pointer Register Name: US_RPR Access Type: Read/Write Reset State: 0 Offset: 0x30 • RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. 18.10.13 USART ...
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USART Transmit Pointer Register Name: US_TPR Access Type: Read/Write Reset State: 0 Offset: 0x38 • TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. 18.10.15 USART ...
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... TC: Timer Counter The AT91M55800A features two Timer Counter Blocks, each containing three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. ...
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Figure 19-1. TC Block Diagram MCK/2 TCLK0 MCK/8 TIOA1 TIOA2 MCK/32 TCLK1 TCLK2 MCK/128 MCK/1024 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 Timer Counter Block 1745F–ATARM–06-Sep-07 XC0 Timer Counter TIOA Channel 0 XC1 TIOB XC2 TC0XC0S SYNC ...
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Signal Name Description Table 19-1. Signal Name Description Channel Signals XC0, XC1, XC2 TIOA TIOB INT SYNC Block 0 Signals TCLK0, TCLK1, TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Block 1 Signals TCLK3, TCLK4, TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 ...
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Timer Counter Description Each Timer Counter channel is identical in operation. The registers for channel programming are listed in 19.2.1 Counter Each Timer Counter channel is organized around a 16-bit counter. The value of the counter is incremented at ...
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Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in ...
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Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of ...
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Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC Channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on TIOA ...
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Figure 19-4. Capture Mode 1745F–ATARM–06-Sep-07 AT91M5880A CPCS LOVRS COVFS LDRBS LDRAS ETRGS TC_IMR TC_SR 169 ...
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Waveform Operating Mode This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). Waveform Operating Mode allows the TC Channel to generate PWM signals with the same frequency and independently programmable duty ...
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The tables below show which parameter in TC_CMR is used to define the effect of each event. Parameter ASWTRG AEEVT ACPC ACPA Parameter BSWTRG BEEVT BCPC BCPB If two or more events occur at the same time, the priority level ...
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Figure 19-5. Waveform Mode Controller AT91M5880A 172 Output Controller Output CPCS CPBS CPAS COVFS ETRGS TC_IMR TC_SR 1745F–ATARM–06-Sep-07 ...
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TC User Interface TC Block 0 Base Address: 0xFFFD0000 (Code Label TCB0_BASE) TC Block 1 Base Address: 0xFFFD4000 (Code Label TCB1_BASE) Table 19-2. TC Global Register Mapping Offset Channel/Register 0x00 TC Channel 0 0x40 TC Channel 1 0x80 TC ...
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TC Block Control Register Register Name: TC_BCR Access Type: Write-only Offset: 0xC0 31 30 – – – – – – – – • SYNC: Synchro Command (Code Label TC_SYNC effect. ...
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TC Block Mode Register Register Name: TC_BMR Access Type: Read/Write Reset State: 0 Offset: 0xC4 31 30 – – – – – – – – • TC0XC0S: External Clock Signal 0 Selection TC0XC0S ...
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TC Channel Control Register Register Name: TC_CCR Access Type: Write-only Offset: 0x00 31 30 – – – – – – – – • CLKEN: Counter Clock Enable Command (Code Label TC_CLKEN ...
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TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type: Read/Write Reset State: 0 Offset: 0x04 31 30 – – – – WAVE=0 CPCTRG 7 6 LDBDIS LDBSTOP • TCCLKS: Clock Selection TCCLKS Clock ...
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LDBDIS: Counter Clock Disable with RB Loading (Code Label TC_LDBDIS Counter clock is not disabled when RB loading occurs Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge ...
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TC Channel Mode Register: Waveform Mode Register Name: TC_CMR Access Type: Read/Write Reset State: 0 Offset: 0x4 31 30 BSWTRG 23 22 ASWTRG 15 14 WAVE=1 CPCTRG 7 6 CPCDIS CPCSTOP • TCCLKS: Clock Selection TCCLKS Clock Selected 0 ...
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CPCDIS: Counter Clock Disable with RC Compare (Code Label TC_CPCDIS Counter clock is not disabled when counter reaches RC Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG Edge ...
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ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 None 0 1 Set 1 0 Clear 1 ...
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BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 ...
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TC Counter Value Register Register Name: TC_CVR Access Type: Read-only Reset State: 0 Offset: 0x10 31 30 – – – – • CV: Counter Value (Code Label TC_CV) CV contains the counter value ...
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TC Register B Register Name: TC_RB Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 Reset State: 0 Offset: 0x18 31 30 – – – – • RB: Register B ...
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TC Status Register Register Name: TC_SR Access Type: Read/Write Offset: 0x20 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow Status (Code Label TC_COVFS counter ...
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CLKSTA: Clock Enabling Status (Code Label TC_CLKSTA Clock is disabled Clock is enabled. • MTIOA: TIOA Mirror (Code Label TC_MTIOA TIOA is low. If WAVE = 0, this means that TIOA pin is ...
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TC Interrupt Enable Register Register Name: TC_IER Access Type: Write-only Offset: 0x24 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow (Code Label TC_COVFS effect. ...
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TC Interrupt Disable Register Register Name: TC_IDR Access Type: Write-only Offset: 0x28 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow (Code Label TC_COVFS effect. ...
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TC Interrupt Mask Register Register Name: TC_IMR Access Type: Read-only Reset State: 0 Offset: 0x2C 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow (Code Label TC_COVFS) 0 ...
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... SPI: Serial Peripheral Interface The AT91M55800A includes an SPI which provides communication with external devices in master or slave mode. The SPI has four external chip selects which can be connected devices. The data length is programmable, from 8- to 16-bit. As for the USART, a 2-channel PDC can be used to move data between memory and the SPI without CPU intervention ...
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Table 20-1. SPI Pins Pin Name Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/ Slave Select Notes: 1. After a hardware reset, the SPI clock is disabled by default. The user must ...
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Variable Peripheral Select Variable Peripheral Select is activated by setting bit PS to one. The PCS field in SP_TDR (Transmit Data Register) is used to select the destination peripheral. The data transfer charac- teristics are changed when the selected ...
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Figure 20-2. Functional Flow Diagram in Master Mode SPI Enable TDRE 0 PS Variable Peripheral 1 NPCS = SP_TDR(PCS) Delay DLYBS Serializer = SP_TDR(TD) TDRE = 1 Data Transfer SP_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT TDRE 1 NPCS ...
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Figure 20-3. SPI in Master Mode SP_MR(MCK32) MCK 0 SPI Master 1 MCK/32 Clock SPIDIS SPIEN MISO SP_MR(PS SP_MR(PCS) AT91M5880A 194 SPCK Clock Generator SP_CSRx[15: SP_RDR PCS RD LSB MSB Serializer SP_TDR PCS TD SP_MR(MSTR) ...
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Slave Mode In Slave Mode, the SPI waits for NSS to go active low before receiving the serial clock from an external master. In slave mode CPOL, NCPHA and BITS fields of SP_CSR0 are used to define the transfer ...
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Data Transfer The following waveforms show examples of data transfers. Figure 20-4. SPI Transfer Format (NCPHA equals One, 8 bits per transfer) SPCK cycle (for reference) 1 SPCK (CPOL=0) SPCK (CPOL=1) MOSI (from master) MSB MISO MSB (from slave) ...
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Figure 20-6. Programmable Delays (DLYBCS, DLYBS and DLYBCT) Chip Select 1 Change peripheral Chip Select 2 SPCK Output 20.5 Clock Generation In master mode the SPI Master Clock is either MCK or MCK/32, as defined by the MCK32 field of ...
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SPI User Interface SPI Base Address: 0xFFFBC000 (Code Label SPI_BASE) Table 20-2. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Receive Data Register 0x0C Transmit Data Register 0x10 Status Register 0x14 Interrupt Enable Register 0x18 Interrupt ...
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SPI Control Register Register Name: SP_CR Access Type: Write-only Offset: 0x00 31 30 – – – – – – – SWRST • SPIEN: SPI Enable (Code Label SP_SPIEN effect. 1 ...
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SPI Mode Register Register Name: SP_MR Access Type: Read/Write Reset State: 0 Offset: 0x04 – – – – – LLB • MSTR: Master/Slave Mode (Code Label SP_MSTR SPI is ...