M55800A Atmel Corporation, M55800A Datasheet - Page 113

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

16. PIO: Parallel I/O Controller
16.1
16.2
16.3
16.4
1745F–ATARM–06-Sep-07
Multiplexed I/O Lines
Output Selection
I/O Levels
Filters
The AT91M55800A has 58 programmable I/O lines. 13 pins are dedicated as general-purpose
I/O pins. The other I/O lines are multiplexed with an external signal of a peripheral to optimize
the use of available package pins. The PIO lines are controlled by two separate and identical
PIO Controllers called PIOA and PIOB. The PIO controller enables the generation of an interrupt
on input change and insertion of a simple input glitch filter on any of the PIO pins.
Some I/O lines are multiplexed with an I/O signal of a peripheral. After reset, the pin is controlled
by the PIO Controller and is in input mode.
When a peripheral signal is not used in an application, the corresponding pin can be used as a
parallel I/O. Each parallel I/O line is bi-directional, whether the peripheral defines the signal as
input or output. Figure 16-1 shows the multiplexing of the peripheral signals with Parallel I/O
signals.
If a pin is multiplexed between the PIO Controller and a peripheral, the pin is controlled by the
registers PIO_PER (PIO Enable) and PIO_PDR (PIO Disable). The register PIO_PSR (PIO Sta-
tus) indicates whether the pin is controlled by the corresponding peripheral or by the PIO
Controller.
If a pin is a general multi-purpose parallel I/O pin (not multiplexed with a peripheral), PIO_PER
and PIO_PDR have no effect and PIO_PSR returns 1 for the bits corresponding to these pins.
When the PIO is selected, the peripheral input line is connected to zero.
The user can enable each individual I/O signal as an output with the registers PIO_OER (Output
Enable) and PIO_ODR (Output Disable). The output status of the I/O signals can be read in the
register PIO_OSR (Output Status). The direction defined has effect only if the pin is configured
to be controlled by the PIO Controller.
Each pin can be configured to be driven high or low. The level is defined in four different ways,
according to the following conditions.
If a pin is controlled by the PIO Controller and is defined as an output (see Output Selection
above), the level is programmed using the registers PIO_SODR (Set Output Data) and
PIO_CODR (Clear Output Data). In this case, the programmed value can be read in PIO_ODSR
(Output Data Status).
If a pin is controlled by the PIO Controller and is not defined as an output, the level is determined
by the external circuit.
If a pin is not controlled by the PIO Controller, the state of the pin is defined by the peripheral
(see peripheral datasheets).
In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status).
Optional input glitch filtering is available on each pin and is controlled by the registers PIO_IFER
(Input Filter Enable) and PIO_IFDR (Input Filter Disable). The input glitch filtering can be
AT91M5880A
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