CY8C3446LTI-085ES2 Cypress Semiconductor Corp, CY8C3446LTI-085ES2 Datasheet - Page 60

• Manufacturer Part Number: CY8C3446LTI-085ES2
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C3446LTI-085ES2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 8-13. Mixer Configuration
8.11 Sample and Hold
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some
applications require multiple signals to be sampled
simultaneously, such as for power calculations (V and I).
Figure 8-14. Sample and Hold Topology
(Φ1 and Φ2 are opposite phases of a clock)
8.11.1 Down Mixer
The SC/CT block can be used as a mixer to down convert an
input signal. This circuit is a high bandwidth passive sample
network that can sample input signals up to 14 MHz. This
sampled value is then held using the opamp with a maximum
clock rate of 4 MHz. The output frequency is at the difference
between the input frequency and the highest integer multiple of
the Local Oscillator that is less than the input.
8.11.2 First Order Modulator – SC Mode
A first order modulator is constructed by placing the SC/CT block
in an integrator mode and using a comparator to provide a 1-bit
feedback to the input. Depending on this bit, a reference voltage
is either subtracted or added to the input signal. The block output
is the output of the comparator and not the integrator in the
modulator case. The signal is downshifted and buffered and then
processed by a decimator to make a delta-sigma converter or a
counter to make an incremental converter. The accuracy of the
Document Number: 001-53304 Rev. *L
V
V
sc_clk
Vin
Vref
n
i
ref
R
mix
0 20 k or 40 k
Φ
Φ
Φ
Φ
2
2
1
1
0
1
C
C
1
3
C2 = 1.7 pF
C1 = 850 fF
Φ
Φ
Φ
Φ
R
2
1
2
mix
1
sc_clk
0 20 k or 40 k
C
C
2
4
Φ
Φ
Φ
Φ
1
2
1
2
V
V
ref
ref
Vout
V
out
sampled data from the first-order modulator is determined from
several factors.
The main application for this modulator is for a low-frequency
ADC with high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement.
9. Programming, Debug Interfaces,
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Three interfaces are available: JTAG, SWD, and SWV. JTAG and
SWD support all programming and debug features of the device.
JTAG also supports standard JTAG scan chains for board level
test and chaining multiple JTAG devices to a single JTAG
connection.
For more information on PSoC 3 Programming, refer to the
application note
PSoC
Complete Debug on Chip (DoC) functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All DOC circuits are disabled by default and can only be enabled
in firmware. If not enabled, the only way to reenable them is to
erase the entire device, clear flash protection, and reprogram the
device with new firmware that enables DOC. Disabling DOC
features, robust flash protection, and hiding custom analog and
digital functionality inside the PSoC device provide a level of
security not possible with multichip application solutions.
Additionally, all device interfaces can be permanently disabled
(Device Security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device. Permanently
disabling interfaces is not recommended in most applications
because you cannot access the device later. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Table 9-1. Debug Configurations
All debug and trace disabled
JTAG
SWD
SWV
SWD + SWV
Debug and Trace Configuration
Resources
®
3.
AN62391 - In-System Programming for
PSoC
®
3: CY8C34 Family
GPIO Pins Used
Data Sheet
Page 60 of 127
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