CY8C3446LTI-085ES2 Cypress Semiconductor Corp, CY8C3446LTI-085ES2 Datasheet - Page 45

• Manufacturer Part Number: CY8C3446LTI-085ES2
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C3446LTI-085ES2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
7.2.3.1 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
7.2.3.2 Clock Generation
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
7.3 UDB Array Description
Figure 7-11
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
Document Number: 001-53304 Rev. *L
shows an example of a 16 UDB array. In addition to
Figure 7-11. Digital System Interface Structure
7.3.1 UDB Array Programmable Resources
Figure 7-12
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
UDB
UDB
UDB
UDB
shows an example of how functions are mapped into
HV
HV
HV
HV
B
A
B
A
UDB
UDB
UDB
UDB
PSoC
System Connections
System Connections
HV
HV
HV
HV
A
B
A
B
®
3: CY8C34 Family
UDB
UDB
UDB
UDB
HV
HV
HV
HV
B
A
B
A
Data Sheet
Page 45 of 127
UDB
UDB
UDB
UDB
HV
HV
HV
HV
A
B
A
B