CY8C3446LTI-085ES2 Cypress Semiconductor Corp, CY8C3446LTI-085ES2 Datasheet - Page 19

• Manufacturer Part Number: CY8C3446LTI-085ES2
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C3446LTI-085ES2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
Document Number: 001-53304 Rev. *L
= 12 cycles
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
function blocks, DMA and
Interrupts 0 to 30
Interrupts form Fixed
from UDBs
Interrupts 0 to
30 from DMA
UDBs
Interrupts 0 to 30
Function Blocks
from Fixed
routing logic
to select 31
Interrupt
sources
Global Enable
Figure 4-3. Interrupt Structure
disable bit
Disable, PEND and
Interrupt Enable/
Enable Disable
POST logic
Individual
bits
30
0
1
interrupts
decoder
8 Level
Priority
for all
Highest Priority
Interrupt Polling logic
Lowest Priority
PSoC
®
3: CY8C34 Family
0 to 30
[15:0]
IRQ
IRA
IRC
ACTIVE_INT_NUM
INT_VECT_ADDR
Data Sheet
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