CY8C3446LTI-085ES2 Cypress Semiconductor Corp, CY8C3446LTI-085ES2 Datasheet - Page 29

• Manufacturer Part Number: CY8C3446LTI-085ES2
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C3446LTI-085ES2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note The two Vccd pins must be connected together with as
short a trace as possible. A trace under the device is
recommended, as shown in
6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Document Number: 001-53304 Rev. *L
Note
Active
Alternate
Active
Sleep
Hibernate
Power Modes
13. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See
Active
Alternat
e Active
Sleep
Hibernat
e
Modes
Active
Alternate Active
Sleep
and
Wakeup
<100 µs
<15 µs
Time
Table
–
–
Primary mode of operation, all
peripherals available (program-
mable)
Similar to Active mode, and is
typically configured to have fewer
peripherals active to reduce
power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
All subsystems automatically
disabled
All subsystems automatically
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
6-3. The power modes allow a design to
1.2 mA
Current
200 nA
(typ)
1 µA
Description
–
Figure 2-6
[13]
Execution
defined
Code
User
on page 10.
Yes
No
No
Resources
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
Digital
None
I
All
All
2
C
Table 11-2
Comparator
Resources
on page 66.
Analog
None
Any interrupt
Any interrupt
Comparator,
PICU, I
CTW, LVD
PICU
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins.
between power modes.
All
All
Sleep
Hibernate
Figure 6-5
2
C, RTC,
Clock Sources
ILO/kHzECO
Available
None
All
All
on page 30 illustrates the allowable transitions
Any
(programmable)
Any
(programmable)
ILO/kHzECO
Active Clocks
PSoC
Wakeup Sources
PICU, I
Comparator,
®
CTW, LVD
3: CY8C34 Family
PICU
2
–
–
All regulators available.
Digital and analog
regulators can be disabled if
external regulation used.
All regulators available.
Digital and analog
regulators can be disabled if
external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled if
external regulation used.
Only hibernate regulator
active.
C, RTC,
Regulator
Data Sheet
Page 29 of 127
XRES, LVD,
Sources
Reset
XRES
WDR
All
All