CY8C3446LTI-085ES2 Cypress Semiconductor Corp, CY8C3446LTI-085ES2 Datasheet - Page 16

• Manufacturer Part Number: CY8C3446LTI-085ES2
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C3446LTI-085ES2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.4 DMA and PHUB
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.4.1 PHUB Features
Table 4-6. PHUB Spokes and Peripherals
4.4.2 DMA Features
Document Number: 001-53304 Rev. *L
PHUB Spokes
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
CPU and DMA controller are both bus masters to the PHUB
Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8, 16, 24, and 32-bit addressing and data
Twenty-four DMA channels
Each channel has one or more Transaction Descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
TDs can be dynamically updated
Eight levels of priority per channel
0
1
2
3
4
5
6
7
SRAM
IOs, PICU,
PHUB local configuration,
Clocks, IC, SWV, EEPROM,
programming interface
Analog interface and
USB, CAN,
Reserved
UDBs group 1
UDBs group 2
EMIF
I
2
C,
Timers, Counters, and PWMs
Peripherals
trim,
Power
Decimator
Flash
manager,
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in
1 have satisfied their requirements.
Table 4-7. Priority Levels
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64 KB
TDs may be nested and/or chained for complex transactions
Priority Level
Table 4-7
0
1
2
3
4
5
6
7
after the CPU and DMA priority levels 0 and
PSoC
% Bus Bandwidth
®
3: CY8C34 Family
100.0
100.0
50.0
25.0
12.5
6.2
3.1
1.5
Data Sheet
Page 16 of 127