KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 64

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

High-Speed Serial Interfaces (HSSI)
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•
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
— The SD_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or
Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
average voltage (common mode voltage) to be between 100 and 400 mV.
SerDes reference clock input requirement for DC-coupled connection scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn).
input requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from V
SD_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for single-ended signaling mode.
AC-coupled externally. For the best noise performance, the reference of the clock could be DC-
or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as
the clock input (SD_REF_CLK) in use.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
200 mV < Input Amplitude or Differential Peak < 800 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
Figure 41
shows the SerDes reference clock
100 mV < V
V
V
max
min
Freescale Semiconductor
Figure 40
< V
> V
V
min
cm
cm
max
Figure 42
cm
+ 400 mV
– 400 mV
V
to V
< 800 mV
< 400 mV
min
shows the
> 0 V
V
max
cm
shows
) with