KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 55

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

13.2
Table 46
Freescale Semiconductor
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
Data setup time
Data input hold time:
Data output delay time:
Set-up time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected
device (including hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. As a transmitter, the MPC8548E provides a delay time of at least 300 ns for the SDA signal (refer to the V
3. The maximum t
4. Guaranteed by design.
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When MPC8548E acts as the I
on SCL and SDA are balanced, MPC8548E would not cause unintended generation of Start or Stop condition. Therefore,
the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required
for MPC8548E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure
both the desired I
frequency is 400 kHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of
0x10 (decimal 16):
I
FDR bit setting
Actual FDR divider selected
Actual I
For the detail of I
Divider Ratio for SCL. Note that the I
2
C source clock frequency
2
provides the AC timing parameters for the I
I
C SCL frequency generated
2
C AC Electrical Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
I2DXKL
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
2
2
C frequency calculation, refer to Freescale Application Note AN2919, Determining the I
C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I
Parameter
has only to be met if the device does not stretch the LOW period (t
CBUS compatible masters
I2SXKL
2
C bus master while transmitting, MPC8548E drives both SCL and SDA. As long as the load
I2C
Table 46. I
symbolizes I
2
clock reference (K) going to the low (L) state or hold time. Also, t
C source clock frequency is half of the CCB clock frequency for MPC8548E.
I
2
371 kHz
333 MHz
0x2A
896
C bus devices
2
C AC Electrical Specifications
2
C timing (I2) for the time that the data with respect to the start condition
266 MHz
0x05
704
378 kHz
Symbol
t
t
t
t
t
t
t
I2PVKH
I2KHDX
I2SVKH
I2DVKH
I2DXKL
I2OVKL
I2SXKL
t
t
V
V
f
I2CH
I2CL
2
I2C
NH
NL
C interfaces.
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
200 MHz
390 kHz
0x26
512
1
0.1 × OV
0.2 × OV
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
—
—
0
0
133 MHz
346 kHz
0x00
384
DD
DD
I2C
clock reference (K) going to the high
I2CL
I2DVKH
Max
400
0.9
—
—
—
—
—
—
—
—
—
—
—
) of the SCL signal.
symbolizes I
I2PVKH
IH
2
Unit
kHz
C Frequency
(min) of the SCL
μs
μs
μs
μs
ns
μs
—
μs
μs
V
V
symbolizes I
2
2
C SCL clock
C timing (I2)
I2C
Notes
—
—
—
—
—
clock
for
4
4
4
4
4
2
3
2
C
I
55
2
C