KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 123

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

19 Clocking
This section describes the PLL configuration of the MPC8548E. Note that the platform clock is identical
to the core complex bus (CCB) clock.
19.1
Table 71
through
Freescale Semiconductor
Note: All note references in this table use the same numbers as those for
notes.
e500 core processor frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
e500 core processor frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
SD_IMP_CAL_TX
Table 76
SD_PLL_TPA
through
Clock Ranges
Signal
Table 71. Processor Core Clocking Specifications (MPC8548E and MPC8547E)
Characteristic
Characteristic
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Table 73
provide the clocking specifications for the memory bus.
Section 19.2, “CCB/SYSCLK PLL Ratio,”
Section 19.2, “CCB/SYSCLK PLL Ratio,”
Table 72. Processor Core Clocking Specifications (MPC8545E)
provide the clocking specifications for the processor cores and
Table 70. MPC8543E Pinout Listing (continued)
Package Pin Number
Min
800
Min
800
1000 MHz
800 MHz
AB26
Maximum Processor Core Frequency
Maximum Processor Core Frequency
U26
1000
Max
Max
800
and
and
Section 19.3, “e500 Core PLL Ratio,”
Section 19.3, “e500 Core PLL Ratio,”
Min
800
Min
800
1200 MHz
1000 MHz
Table
67. Refer to
1200
1000
Max
Max
Pin Type
Min
800
Min
800
1333 MHz
1200 MHz
O
Table 67
I
1333
1200
Max
Max
for the meanings of these
AVDD_SRDS
100 Ω (±1%)
Supply
to GND
Power
for ratio settings.
for ratio settings.
MHz
MHz
Unit
Unit
Table
74,
Notes
Notes
Clocking
Notes
1, 2
1, 2
24
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