KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 28

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Enhanced Three-Speed Ethernet (eTSEC)
A summary of the FIFO AC specifications appears in
Timing diagrams for FIFO appear in
28
TX_CLK, GTX_CLK clock period
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Note:
1. The minimum cycle period of the TX_CLK and RX_CLK is dependent on the maximum platform frequency of t he speed bins
the part belongs to as well as the FIFO mode under operation. Refer to
GTX_CLK
TXD[7:0]
TX_EN
TX_ER
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Parameter/Condition
Parameter/Condition
Table 24. FIFO Mode Transmit AC Timing Specification
Table 25. FIFO Mode Receive AC Timing Specification
t
FITH
Figure 6. FIFO Transmit AC Timing Diagram
t
FIT
Figure 6
t
FITDV
and
Figure
Table 24
t
FITF
7.
t
t
t
Symbol
Symbol
FITDX
FIRH
FITH
t
t
t
t
t
FITDX
t
t
FIRDV
FIRDX
t
FITDV
t
t
t
FIRR
t
FITR
FITF
FIRJ
FIRF
FITJ
Section 4.5, “Platform to FIFO Restrictions.”
FIR
FIT
and
/t
/t
FIT
FIR
Table
Min
Min
5.3
2.0
0.5
5.3
1.5
0.5
45
45
—
—
—
—
—
—
25.
Typ
Typ
8.0
8.0
50
50
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
t
FITR
Max
0.75
0.75
Max
0.75
0.75
100
250
100
250
3.0
55
55
—
—
—
Unit
Unit
ns
ps
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
%
%