KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 141

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
Revision
3
2
01/2009
04/2008
Date
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
•
• In
•
•
• In
• In
• In
• In
• In
• In
• In
• In
• In
• Added new section,
•
•
• Added information to
•
•
• Removed 1:1 support on
• Removed MDM from
•
•
• Split
[Section 4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.”
minimum frequency equation to be 527 MHz for PCI x8.
Section 4.5, “Platform to FIFO Restrictions.”
Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics.”
and add ‘or 2.5 V’ after 3.3 V.
TSECn_TX_CLK.
high from 32 to 48 ns.
Section 16.1, “DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK.”
paragraph.
Section 17.1, “DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK.”
paragraph.
Section 21.3, “Decoupling Recommendations.”
Table 83, “Part Numbering Nomenclature.”
Figure 56, “PLL Power Supply Filter Circuit with PLAT
Figure 57, “PLL Power Supply Filter Circuit with CORE
Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two
new ones.
Table
Table
Table 24
Table
Table
Table 30
Section 8.2.5, “TBI Single-Clock Mode AC Specifications.”
Table
Table
Table
Figure 58, “PLL Power Supply Filter Circuit with PCI/LBIU
5, added note 7.
23, modified table title to include GMII, MII, RMII, and TBI.
25, added a note.
26,
34,
36, changed all instances of OV
37, “MII Management AC Timing Specifications,” changed MDC minimum clock pulse width
Table 84. Document Revision History (continued)
and
and
Table
Table
Table
Figure
27,
35,
Section 15, “High-Speed Serial Interfaces (HSSI).”
Table 18, “DDR SDRAM Input AC Timing
Figure
25, changed clock period minimum to 5.3.
Table
Figure
15, changed all instances of PMA to TSECn.
Table 78, “e500 Core to CCB Clock
28,
63, both in figure and in note.
18, and
Table
Substantive Change(s)
Figure
29, and
DD
In Silicon Version column added Ver. 2.1.2.
to LV
20, changed all instances of REF_CLK to
Changed platform clock frequency to 4.2.
Table
Modified the recommendation.
DD
/TV
30, removed subtitle from table title.
Pins” (AVDD_PLAT).
DD
Pins” (AVDD_CORE).
.
Replaced first paragraph.
Ratio.”
Pins,” (formerly called just “PLL Power
Specifications.” MDM is an Output.
Document Revision History
Added MII after GMII
Added new
Changed
Added new
141