KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 140

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Document Revision History
23 Document Revision History
Table 84
140
Revision
7
6
5
4
provides a revision history for the MPC8548E hardware specification.
09/2010
12/2009
10/2009
04/2009
Date
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
• In
• In
• Updated
• In
• In
• In
• In
• In
• In
• Updated tMDKHDX in
• Added a reference to Revision 2.1.2.
• Updated
• Added
• In
• In
• In
• Modified
• Modified DDR clk rate min from 133 to 166 MHz.
• Modified note in
• In
• In
• Modified
• Added a note on
• In
• Added note to
row from “(16 × tptb_clk × 8) – 3” and “(16 × tptb_clk × 8) + 3” to “(16 × tCCB × 8) – 3” and “(16 × tCCB
× 8) + 3.”
FC-CBGA and FC-PBGA with Full Lid,” and figure notes.
avoid falsely triggering ESD circuitry.
for MVREF and 4000 V/s for VDD.
AVDD pins.
35/75 for RX_CLK duty cycle.
moved text, “MII management voltage” from LV
OVDD row of input voltage section.
time.
OV
column, and changed all instances of “LO” to “L0.” In addition, added note 8.
and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “T
frequency is less than 1200 MHz
Pinout
Table
Table 67–Table
Section 5.1, “Power-On Ramp
Table 10
Table 10
Table 10
Table 10
Table
Table
Table
Table
Table 52,
Table 53,
Table 67,
DD
.
ListingTable 70,
Section 5.1, “Power-On Ramp
37, “MII Management AC Timing Specifications,” modified the min and max columns in the fifth
27, ”GMII Receive AC Timing Specifications,” changed duty cycle specification from 40/60 to
1, “Absolute Maximum Ratings
5, “SYSCLK AC Timing Specifications,” added notes 7 and 8 to SYSCLK frequency and cycle
36, “MII Management DC Electrical Characteristics,” changed all instances of LV
Figure
Table 55,
Section 15, “High-Speed Serial Interfaces
Table
changed required ramp rate from 545 V/s for MVREF and VDD/XVDD/SVDD to 3500 V/s
deleted ramp rate requirement for XVDD/SVDD.
footnote 1 changed voltage range of concern from 0–400 mV to 20–500mV.
added footnote 2 explaining that VDD voltage ramp rate is intended to control ramp rate of
“Differential Receiver (RX) Input Specifications,” modified equations in Comments column,
“Differential Transmitter (TX) Output Specifications,” modified equations in Comments
“MPC8548E Pinout
Table
79, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”
55, “Mechanical Dimensions and Bottom Surface Nomenclature of the HiCTE
Table 84. Document Revision History
Table
Section 4.1, “System Clock
70, added note 114 to table and LGPL4/LGTA/LUPWAIT/LPBSE row.
“MII Management AC Timing Specifications.”
79, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”
Table
71, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “.”
“MPC8543E Pinout Listing,” added note 5 to LA[28:31].
37, “MII Management AC Timing Specifications.”
ListingTable 68,
Rate” added explanation that Power-On Ramp Rate is required to
Substantive Change(s)
Rate.”
1
,” and in
Timing,” to limit the SYSCLK to 100 MHz if the core
DD
“MPC8547E Pinout
Table
/TV
(HSSI),” to reflect that there is only one SerDes.
DD
2, “Recommended Operating Conditions,”
to OV
DD
, added “Ethernet management” to
RX-EYE-MEDIAN-to-MAX-JITTER
ListingTable 69,
Freescale Semiconductor
“MPC8545E
DD
/OV
.”
DD
to