UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 464

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

462
Call/return
Stack
manipu-
late
Uncondi-
tional
branch
Conditional
branch
Instruction
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access is executed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2. When an area except the internal high-speed RAM area is accessed
CALL
CALLF
CALLT
BRK
RET
RETI
RETB
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
Mnemonic
2. The number of clocks applies when there is a program in the internal ROM.
register (PCC).
!addr16
!addr11
[addr5]
PSW
rp
PSW
rp
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Operands
CHAPTER 24 INSTRUCTION SET
User’s Manual U14260EJ4V0UD
Bytes
3
2
1
1
1
1
1
1
1
1
1
4
2
2
3
2
2
2
2
2
2
Note 1
7
5
6
6
6
6
6
2
4
2
4
–
–
–
6
6
8
6
6
6
6
Clocks
Note 2
10
–
–
–
–
–
–
–
–
–
–
–
8
8
–
–
–
–
–
–
–
(SP – 1)
PC
(SP – 1)
PC
SP
(SP – 1)
PC
PC
SP
(SP – 1)
(SP – 3)
PC
PC
SP
PC
PSW
PC
PSW
(SP – 1)
(SP – 1)
SP
PSW
rp
SP
SP
SP
AX
PC
PC
PC
PC
PC
PC
PC
H
15 – 11
H
L
L
H
H
H
H
addr16, SP
SP – 2
SP – 2
SP + 2
SP – 2
(SP + 1), rp
SP + 2
word
AX
SP
addr16
PC + 2 + jdisp8
PC + 2 + jdisp8 if CY = 1
PC + 2 + jdisp8 if CY = 0
PC + 2 + jdisp8 if Z = 1
PC + 2 + jdisp8 if Z = 0
(00000000, addr5),
(003EH), SP
(00000000, addr5 + 1),
(SP + 1), PC
(SP + 1), PC
(SP + 1), PC
A, PC
CPU
(SP + 2), SP
(SP + 2), SP
(SP), SP
(PC + 3)
(PC + 2)
(PC + 1)
00001, PC
) selected by the processor clock control
PSW, (SP – 2)
(PC + 1)
PSW, SP
rp
L
H
, (SP – 2)
Operation
X
L
H
H
H
, (SP – 2)
, (SP – 2)
, (SP – 2)
L
L
L
L
SP + 1
, PC
SP – 2
10 – 0
(SP),
SP – 3, IE
(SP),
(SP),
(SP),
SP – 1
SP + 3
SP + 3
H
rp
addr11,
(PC + 1)
(003FH),
L
,
(PC + 3)
(PC + 2)
(PC + 1)
0
H
,
L
L
L
,
,
,
R
R
R
Z AC CY
Flag
R
R
R
R
R
R