UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 303

no-image

UPD78F0078GK-9ET-A

Manufacturer Part Number
UPD78F0078GK-9ET-A
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0078GK-9ET-A

Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0078GK-9ET-A
Quantity:
57
Figure 15-22. Timing of Receive Completion Interrupt Request in Multi-Processor Transfer Mode (1/2)
(c) Reception
(1) If receive data matches ID
The interface enters the reception wait status if the multi-processor transfer mode is specified by using
transfer mode specification register 2 (TRMC2) and bit 7 (POWER2) of asynchronous serial interface mode
register 2 (ASIM2) is set to 1 and then bit 5 (RXE2) is set to 1. In this status, the R
to detect the start bit. When the start bit is detected, reception is started, and serial data is sequentially
stored in receive shift register 2 (RX2) at the specified baud rate.
If data with the multi-processor appended bit set to “1” is received (ID reception), a receive completion
interrupt (INTSR2) occurs after the stop bit has been detected and, at the same time, the data in RX2 is written
to receive buffer register 2 (RXB2). At this time, bit 3 (MPR2) of asynchronous serial interface register 2
(ASIS2) is set to 1. After it has been confirmed that MPR2 is 1, the ID of the receive data and the ID of
the microprocessor are compared (for which software processing is necessary). If the two IDs match, the
interface prepares for the next reception and waits for the next receive completion interrupt (INTSR2). If
the IDs do not match, clear bit 1 (MPIEN2) of transfer mode specification register 2 (TRMC2) to 0. This makes
receive data other than ID invalid and prevents occurrence of an unwanted receive completion interrupt
(INTSR2).
RxD2 (input)
MPIEN2
INTSR2
MPR2
RXB2
CPU
1
Start
CHAPTER 15 SERIAL INTERFACE UART2
D0
ID receive frame
FF
User’s Manual U14260EJ4V0UD
D7
MPR2
Stop
MPR2
Start
1
Data receive frame
D0
IDs match. Prepares for reception and
waits for INTSR2.
Data 1 (ID)
RXB2
D7
MPR2
data 1 (ID)
Stop
Start
Data 2 (data)
X
D2 pin is monitored
data 2 (data)
RXB2
D0
301

Related parts for UPD78F0078GK-9ET-A