UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 141

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.5.1 Main system clock operations
0), the following operations are carried out by PCC setting.
(a) Because the operation-guaranteed instruction execution speed depends on the power supply voltage, the
(b) When bit 4 (CSS) of PCC is set to 1 when operating with the main system clock, if bit 7 (MCC) of PCC is set
(c) If bit 7 (MCC) of PCC is set to 1 when operating with the main system clock, the main system clock oscillation
When operating with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to
minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of PCC.
to 1 after the operation has been switched to the subsystem clock (CLS = 1), the main system clock oscillation
stops (see Figure 7-8 (1)).
does not stop. When bit 4 (CSS) of PCC is set to 1 and the operation is switched to the subsystem clock (CLS
= 1) after that, the main system clock oscillation stops (see Figure 7-8 (2)).
(1) Operation when MCC is set after setting CSS with main system clock operation
(2) Operation when CSS is set after setting MCC with main system clock operation
Main system clock oscillation
Main system clock oscillation
Subsystem clock oscillation
Subsystem clock oscillation
CPU clock
CPU clock
Figure 7-8. Main System Clock Stop Function
MCC
MCC
CSS
CSS
CLS
CLS
CHAPTER 7 CLOCK GENERATOR
Oscillation does not stop
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