UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 343

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Remark Bit 1 (STT0) is 0 when read after data has been set.
Cautions concerning set timing
• For master reception:
• For master transmission: A start condition may not be generated normally during the acknowledgment period.
• Cannot be set at the same time as SPT0.
Condition for clearing (STT0 = 0)
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• When RESET is input
STT0
device
0
1
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
Do not generate a start condition.
When bus is released (during STOP mode):
Generate a start condition (for starting as master). The SDA0 line is changed from high level to low
level and then the start condition is generated. Next, after the rated amount of time has elapsed,
SCL0 is changed to low level.
When bus is not used:
This trigger functions as a start condition reservation flag. When set, it releases the bus and then
automatically generates a start condition.
Wait status (during master mode):
Generate a restart condition after wait is released.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (3/4)
Cannot be set during transfer. Can be set only in the waiting period when ACKE0
has been set to 0 and slave has been notified of final reception.
Therefore, set it during the waiting period.
User’s Manual U14260EJ4V0UD
Start condition trigger
Condition for setting (STT0 = 1)
• Set by instruction
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