UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 235

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UPD78F0078GK-9ET-A

Manufacturer Part Number
UPD78F0078GK-9ET-A
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0078GK-9ET-A

Lead Free Status / Rohs Status
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A/D converter
operation
is reset (0) by software.
conversion operation, the conversion operation is initialized, and if ADCS0 is set (1), conversion starts again from
the beginning.
A/D conversion operations are performed continuously until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0)
If a write operation is performed to ADM0 or analog input channel specification register 0 (ADS0) during an A/D
RESET input sets A/D conversion result register 0 (ADCR0) to 0000H.
Confirm the conversion results by referring to the A/D conversion end interrupt request flag (ADIF0).
INTAD0
ADCR0
ADCS0
SAR
Setting ADCS0 to 1, external trigger,
or overwriting ADS0
Undefined
Sampling
Sampling time
A/D conversion start delay time
200H
Figure 13-7. Basic Operation of A/D Converter
300H
100H
or
CHAPTER 13 A/D CONVERTER
User’s Manual U14260EJ4V0UD
Conversion time
A/D conversion
Conversion
result
Conversion
result
233

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