B69000 Asiliant Technologies, B69000 Datasheet - Page 315

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

B-2
PLL Parameters
Each phase-locked loop consists of the elements shown in the figure below. The reference input frequency
(14.31818MHz) is divided by N, a 8-bit programmable value. The output of the VCO is divided by 1 (or 4
via the VCO Loop Divider: VLD) and then further divided by M, another 8-bit programmable value. The
phase detector compares the N and M results and adjusts the VCO frequency as needed to achieve
frequency equality.
When the loop has stabilized, the VCO frequency (F
For VLD =1, the F
The VCO output can be further divided by 1, 2, 4, 8, 16, or 32 (which is called Post Divisor: PD) to produce
the final DCLK or MCLK used for video or memory timing.
Therefore the output frequency is:
By “fine tuning” the M/N ratio in each PLL, extremely small adjustments in the exact DCLK and MCLK
frequencies can be achieved. The VCO itself is designed to operate in the range of 100MHz to 220 MHz.
&+,36
R EF C L K
14 .3 M H z
If VLD=1:
If VLD=4:
(DCLK only)
69000 Databook
M counter = Program value M’+2
N counter = Program value N’+2
VCO
N
÷
can be written as:
or
D etect
Phase
÷M
Subject to Change Without Notice
Figure B-1: PLL Elements
F
F
F
F
VCO
VCO
VCO
OUT
C harge Pum p
Clock Generation
(D C LK o nly)
D ivide (VLD )
VC O Loop
& Filter
(÷4, ÷1)
= (F
/M = F
/4M = F
= (F
VCO
REF
VCO
REF
REF
)/PD
) is related to the reference as follows:
*M /N)
F
/ N
F
OUT
/ N.
VCO
: Output frequency: (desired frequency)
: VCO frequency (before post divisor)
VC O
F
VCO
Post D ivisor
8, 16, 32
÷1, 2, 4,
(PD )
Revision 1.3 8/31/98
F
OUT
C LK