B69000 Asiliant Technologies, B69000 Datasheet - Page 31

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PCI/AGP Bus Interface (continued)
&+,36
BGA mBGA
PIN
G2
M4
M3
J2
H2
G3
F2
D1
P3
M2
F1
U2
T3
R4
T2
U1
T1
N3
N2
N1
J4
G1
H3
E1
E3
K3
R3
R2
R1
P2
P1
J1
H1
J3
F3
E2
F4
PIN
G1
G3
M4
M3
M2
G4
D1
E3
G5
C2
D3
M1
G2
P1
N2
N1
K5
K3
K1
H4
H5
D2
F5
L5
L4
L3
L2
L1
K2
K4
F2
F1
E2
F4
F3
69000 Databook
E1
J6
Pin
Name
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IDSEL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
In
In
In
In
In
Active
Subject to Change Without Notice
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Pin Descriptions
Powered
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Description
PCI/AGP Address/Data Bus
Address and data are multiplexed on the same pins. A
bus transaction consists of an address phase followed
by one or more data phases (both read and write
bursts are allowed by the bus definition).
The address phase is the clock cycle in which
FRAME# is asserted (AD0-31 contain a 32-bit physical
address). For I/O, the address is a byte address. For
memory and configuration, the address is a DWORD
address. During data phases AD0-7 contain the LSB
and 24-31 contain the MSB. Write data is stable and
valid when IRDY# is asserted; read data is stable and
valid when TRDY# is asserted. Data transfers only
during those clocks when both IRDY# and TRDY# are
asserted.
Bus Command/Byte Enables. During the address
phase of a bus transaction, these pins define the bus
command (see list above). During the data phase,
these pins are byte enables that determine which byte
lanes carry meaningful data: byte 0 corresponds to
AD0-7, byte 1 to 8-15, byte 2 to 16-23, and byte 3 to
24-31.
Initialization Device Select. Used as a chip select dur-
ing configuration read and write transactions
C/BE3-0 Command Type
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
-reserved-
-reserved-
Memory Read
Memory Write
-reserved-
-reserved-
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Read & Invalidate
Revision 1.3 8/31/98
Supported
Y
Y
Y
Y
Y
Y
2-7