B69000 Asiliant Technologies, B69000 Datasheet - Page 210

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

XRCC
read/write at I/O address 3D7h with index at I/O address 3D6h set to CCh
Note: All three of the registers used in specifying the loop parameters for the memory clock (XRCC -
XRCE) must be written, and in order from XRCC to XRCE, before the hardware will update the synthesizer’s
settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output
as new values are being written to these registers.
7-0
XRCD
read/write at I/O address 3D7h with index at I/O address 3D6h set to CDh
Note: All three of the registers used in specifying the loop parameters for the memory clock (XRCC -
XRCE) must be written, and in order from XRCC to XRCE, before the hardware will update the synthesizer’s
settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output
as new values are being written to these registers.
7-0
&+,36
7
7
Memory Clock VCO M-Divisor
These eight bits specify the M-divisor, one of the loop parameters used in controlling the frequency
of the output of the synthesizer used to generate the memory clock.
A series of calculations are used to derive this value and the values for the other loop parameters
given a desired output frequency and a series of constraints placed on different components within
the synthesizer used to generate the memory clock. See appendix B for a detailed description of
the process used to derive the loop parameter values.
Memory Clock VCO N-Divisor
These eight bits specify the N-divisor, one of the loop parameters used in controlling the frequency
of the output of the synthesizer used to generate the memory clock.
A series of calculations are used to derive this value and the values for the other loop parameters
given a desired output frequency and a series of constraints placed on different components within
the synthesizer used to generate the memory clock. See appendix B for a detailed description of
the process used to derive the loop parameter values.
69000 Databook
Memory Clock VCO M-Divisor Register
Memory Clock VCO N-Divisor Register
6
6
5
5
Subject to Change Without Notice
Memory Clock VCO M-Divisor
Memory Clock VCO N-Divisor
Extension Registers
4
4
3
3
2
2
Revision 1.3 8/31/98
1
1
0
0
14-43