B69000 Asiliant Technologies, B69000 Datasheet - Page 115

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-22
CR12
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 12h
7-0
CR13
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 13h
7-0
&+,36
7
7
Vertical Display Enable End Bits 7-0
This register provides the 8 least significant bits of either a 10-bit or 12-bit value that specifies the
number of the last scanline within the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, this value is
described in 10 bits with bits 6 and 1 of the Overflow Register (CR07) supplying the 2 most
significant bits.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, this value is described
in 12 bits with bits 3-0 of the Extended Vertical Display Enable End Register (CR31) supplying the
4 most significant bits.
This 10-bit or 12-bit value should be programmed to be equal to the number of the last scanline
within in the active display area. Since the active display area always starts on the 0th scanline,
this number should be equal to the total number of scanlines within the active display area, minus 1.
Offset Bits 7-0
This register provides either all 8 bits of an 8-bit value or the 8 least significant bits of a 12-bit value
that specifies the number of words or doublewords of frame buffer memory occupied by each
horizontal row of characters. Whether this value is interpreted as the number of words or
doublewords is determined by the settings of the bits in the Clocking Mode Register (SR01).
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the offset is
described with an 8-bit value, with all the bits provided by this register (CR13).
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the offset is described
with a 12-bit value. The four most significant bits of this value are provided by bits 3-0 of the
Extended Offset Register (CR41), and the eight least significant bits are provided by this register
(CR13).
This 8-bit or 12-bit value should be programmed to be equal to either the number of words or
doublewords (depending on the setting of the bits in the Clocking Mode Register, SR01) of frame
buffer memory that is occupied by each horizontal row of characters.
69000 Databook
Vertical Display Enable End Register
Offset Register
6
6
5
5
Subject to Change Without Notice
Vertical Display Enable End Bits 7-0
CRT Controller Registers
4
4
Offset Bits 7-0
3
3
2
2
Revision 1.3 8/31/98
1
1
0
0