M69000 Asiliant Technologies, M69000 Datasheet
M69000
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69000 69000 HiQVideo Accelerator with Integrated Memory Data Sheet Revision 1.3 August 1998 Y ...
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Copyright Notice Copyright 1997-98 Chips and Technologies, Inc., a subsidiary of Intel Corporation. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc., a subsidiary of Intel Corporation. You may not reproduce, transmit, transcribe, store in a retrieval ...
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High Performance Flat Panel / CRT HiQVideo Accelerator with T Highly integrated Flat Panel and CRT GUI Accelerator & Multimedia Engine, Palette/DAC, Clock Synthesizer, and integrated frame buffer T Integrated High Performance SDRAM memory • 2MB integrated memory • ...
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Software Support Features T Drivers Features • High Performance Accelerated drivers • Compatible across HiQVideo family • Auto Panning Support • LCD/CRT/Simultaneous Mode Support • Auto Resolution Change • HW Stretching/Scaling • Double Buffering • Internationalization • ChipsCPL (Control ...
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Revision History Revision Date 0.1 2/28/97 0.2 4/3/97 1.0 8/18/97 1.1 10/10/97 1.2 3/9/98 1.3 7/1/98 &+,36 69000 Databook By Comments TE/lc/bjb First Draft- Official Release AS/bjb Change MCLK from 110MHz to 83MHz Added HiQColor(features) Updated Pin Descriptions Updated Extension ...
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Databook Subject to Change Without Notice Revision 1.3 8/31/98 ...
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List Of Figures .................................................................................................................................. xv List of Tables ................................................................................................................................... xvii Chapter 1 Introduction / Overview High Performance Integrated Memory ...................................................................................... 1-1 Frame-Based AGP Compatibility .............................................................................................. 1-1 HiQColor Technology ........................................................................................................... 1-1 Versatile Panel Support ........................................................................................................... 1-1 Acceleration for All Panels and ...
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Chapter 5 I/O and Memory Address Maps I/O and Memory Address Map ................................................................................................. 5-1 VGA-Compatible Address Map ................................................................................................. 5-1 Address Maps for Going Beyond VGA...................................................................................... 5-2 PCI Configurations Registers ................................................................................................... 5-3 I/O and Sub-Addressed Register Map ..................................................................................... 5-4 Sub-Addressing ...
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Chapter 9 CRT Controller Registers CRX CRT Controller Index Register .................................................................................. 9-2 CR00 Horizontal Total Register ........................................................................................... 9-3 CR01 Horizontal Display Enable End Register .................................................................... 9-3 CR02 Horizontal Blanking Start Register ............................................................................. 9-3 CR03 Horizontal Blanking End Register .............................................................................. 9-4 ...
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Chapter 10 Sequencer Registers SRX Sequencer Index Register ....................................................................................... 10-2 SR00 Reset Register ......................................................................................................... 10-2 SR01 Clocking Mode Register ........................................................................................... 10-3 SR02 Plane Mask Register ................................................................................................ 10-4 SR03 Character Map Select Register ................................................................................ 10-5 SR04 Memory Mode Register ............................................................................................ ...
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XR0A Frame Buffer Mapping Register ............................................................................... 14-9 XR0B PCI Burst Write Support Register .......................................................................... 14-12 XR0E Frame Buffer Page Select Register ....................................................................... 14-12 XR20 BitBLT Configuration Register ................................................................................ 14-13 XR40 Memory Access Control Register ........................................................................... 14-14 XR41-XR4F Memory Configuration Registers ...
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FR03 FP Dot Clock Source Register ................................................................................. 15-3 FR04 Panel Power Sequencing Delay Register ................................................................ 15-4 FR05 Power Down Control 1 Register ............................................................................... 15-5 FR06 FP Power Down Control Register ............................................................................ 15-6 FR08 FP Pin Polarity Register ........................................................................................... 15-7 ...
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MR05 Capture Control 4 Register ...................................................................................... 16-6 MR06 Capture Memory Address PTR1 Low Register ....................................................... 16-7 MR07 Capture Memory Address PTR1 Mid Register ........................................................ 16-7 MR08 Capture Memory Address PTR1 High Register ....................................................... 16-7 MR09 Capture Memory Address PTR2 Low ...
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BR07 Destination Address Register ................................................................................. 17-13 BR08 Destination Width & Height Register ...................................................................... 17-14 BR09 Source Expansion Background Color & Transparency Key Register .................... 17-15 BR0A Source Expansion Foreground Color Register ...................................................... 17-16 Chapter 18 Memory-Mapped Wide Extension Registers ...
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Appendix E BitBLT Operation .......................................................................................................................... E-1 Introduction ............................................................................................................................. E-1 Color Depth Configuration and Color Expansion .................................................................... E-2 Graphics Data Size Limitations ............................................................................................... E-3 Bit-Wise Operations ................................................................................................................ E-3 Per-Pixel Write-Masking Operations ....................................................................................... E-7 When the Source and Destination Locations Overlap ............................................................ ...
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Databook Subject to Change Without Notice Revision 1.3 8/31/98 ...
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List Of Figures Figure 1-1: Pixel Averaging Circuit ..........................................................................................1-2 Figure 1-3: Data Pipeline After MMUX, 2 Clocking .................................................................. 1-4 Figure 2-1: Pin Diagram, Top View, Ball Grid Array................................................................. 2-1 Figure 2-2: Pin Diagram, Bottom View, Ball Grid Array ........................................................... 2-2 ...
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Databook Subject to Change Without Notice Revision 1.3 8/31/98 ...
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List of Tables Table 1-1: 69000 Mode Support .............................................................................................. 1-4 Table 3-1: Absolute Maximum Conditions .............................................................................. 3-1 Table 3-2: Normal Operating Conditions ................................................................................. 3-1 Table 3-3: DAC Characteristics ...............................................................................................3-1 Table 3-4: DC Characteristics ................................................................................................. 3-2 Table 3-5: DC Drive Characteristics ...
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Databook Subject to Change Without Notice Revision 1.3 8/31/98 ...
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Chapter 1 Introduction / Overview The 69000 is the first product in the CHIPS family of portable graphics accelerator product line that integrates high performance memory technology for the graphics frame buffer. Based on the proven HiQVideo graphics accelerator core, ...
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Flicker reduction can be accomplished by averaging the contents of successive horizontal and vertical lines. See Figure 1-1. The flicker reduction circuit is in pixel data path, with the vertical averaging circuit followed by the horizontal averaging circuit. Both ...
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The television output circuitry supports both NTSC and PAL standard formats, and scales images appropriately for both television formats and panels. HiQVideo Multimedia Support The 69000 uses independent multimedia capture and display systems on-chip. The capture system places data in ...
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Display Modes Supported The 69000 supports the modes which appear in the table below. Resolution 640x480 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1280x1024 &+,36 69000 Databook Introduction / Overview Table 1-1: 69000 Mode Support Color (bpp) Refresh Rates ...
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Chapter 2 Pin Descriptions Pin Diagram, Top View CFG4 CFG2 N/C N/C N/C N/C 20 CFG6 CFG5 CFG1 N/C N/C N/C 19 N/C CFG7 CFG3 CFG0 N/C N/C 18 RMA2 N/C CFG8 TMD0 N/C ...
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Pin Diagram, Bottom View RSVD VP10 VP6 VP1 N/C N/C 20 VP14 VP11 VP9 VP5 VP2 N/C 19 VCLK VP15 VP13 VP8 VP4 VP0 18 P33 HREF PCLK VP12 VP7 VP3 MEMGND MEMVCC ...
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Pin Diagram, Top View MCK DCK A DCLKIN GPIO7 ROMOE# GND GND REF DCK B RSVD N/C INT# CLK VCC BUS STND DCK C AD30 N/C CLK BY GND MCK D AD26 AD24 AD31 N/C ...
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Pin Diagram, Bottom View N/C N/C TMD0 CFG0 CFG3 B N/C N/C N/C CFG4 CFG9 C N/C N/C N/C N/C CFG5 MEM D N/C N/C N/C CFG6 GND MEM E N/C N/C N/C ...
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PCI/AGP Bus Interface BGA mBGA Pin Name Type PIN PIN C1 E4 RESET BUSCLK M1 J2 PAR K2 H3 FRAME IRDY TRDY# S/ STOP# S/TS Note: S/TS stands for “Sustained Tri-state”. These ...
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PCI/AGP Bus Interface (continued) BGA mBGA Pin Name Type PIN PIN L4 J5 DEVSEL# S/ PERR# S/ SERR INT# OD Note: S/TS stands for “Sustained Tri-state”. These signals are driven by only ...
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PCI/AGP Bus Interface (continued) BGA mBGA Pin Type PIN PIN Name U2 P1 AD0 I AD1 I AD2 I AD3 I AD4 I AD5 I AD6 I/O R2 ...
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Configuration Pins and ROM Interface BGA mBGA Pin Name PIN PIN D18 A13 CFG0 C19 E12 CFG1 B20 F12 CFG2 C18 A12 CFG3 A20 B13 CFG4 B19 C12 CFG5 A19 D12 CFG6 B18 F11 CFG7 C17 A11 CFG8 D16 ...
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Flat Panel Display Interface BGA mBGA Pin Type PIN PIN Name Out Out Out Out Out Out Out U9 ...
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Flat Panel Display Interface (continued) BGA mBGA Pin Name Type PIN PIN Y5 T4 SHFCLK OUT W5 L7 FLM OUT (CL1)(DE) OUT (BLANK (DE) OUT (BLANK ENAVDD I ENAVEE ...
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Flat Panel Display Interface (continued) Mono Mono Mono Color TFT Pin 9/12/16 8-bit 8-bit 16 bit Name bit P0 D0 UD3 UD7 UD2 UD6 UD1 UD5 UD0 UD4 ...
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CRT Interface BGA mBGA Pin Name Type PIN PIN U3 K7 HSYNC Out (CSYNC VSYNC Out Y3 K6 RED Out V4 P4 GREEN Out W3 T2 BLUE Out W2 T1 RSET DDC DATA I/O ...
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Video Interface BGA mBGA Pin Name Type PIN PIN V16 T12 VREF I/O W17 M13 HREF In Y18 R13 VCLK In PCLK V17 N12 Out (VCLKOUT) R18 N15 VP0 In U20 T15 VP1 In T19 P16 VP2 In R17 M16 ...
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Miscellaneous BGA mBGA Pin Name Type PIN PIN E4 C3 STNDBY REFCLK In (MCLKIN DCLKIN MCLKIN GPIO0 (ACTI) I GPIO1 I/O (32KHz) U16 P13 GPIO4 I/O ...
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Power and Ground BGA mBGA Pin Name PIN PIN U5 R3 DACVCC Analog power for the internal RAMDAC DACGND Analog ground for the internal RAMDAC MCKVCC Analog power and ground pins for the internal A2 A2 ...
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M9 P3 RGND Internal reference GND, should be tied to GND. M10 M11 M12 IOVCC I/O Power U13 K11 K12 K13 L11 L12 N9 L6 D13 F10 MEMVCC Power ...
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Reserved and No Connect BGA mBGA Pin Name PIN PIN A1 B1 Reserved Y20 A10 C8 No Connect A11 C13 A18 D13 B11 E13 B17 F13 C11 B14 C16 C14 C20 A15 D10 B15 ...
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Databook Pin Descriptions Subject to Change Without Notice Revision 1.3 8/31/98 ...
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Chapter 3 Electrical Specifications Table 3-1: Absolute Maximum Conditions Symbol Parameter V Supply Voltage CC V Input Voltage I T Storage Temperature STG Note: Permanent device damage may occur if Absolute Maximum Rating are exceeded. Operation must be restricted to ...
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Table 3-4: DC Characteristics. Symbol Parameter Power Dissipation Input Leakage Current IL I Output Leakage Current OZ V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage ...
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Table 3-6: AC Test Conditions: Symbol Parameter V Supply Voltage CC V All AC parameters TEST V Input low voltage (10 Input high voltage (90 Maximum input rise time (3.3/5V) R ...
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Table 3-7: AC Timing Characteristics - Reference Clock Symbol Parameter F Reference Frequency REF T Reference Clock Period REF T /T Reference Clock Duty Cycle HI REF Reference Clock Input Table 3-8: AC Timing Characteristics - Clock Generator Symbol ...
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Table 3-9: AC Timing Characteristics - Reset Symbol Parameter T Reset Inactive from Power Stable IPR T Reset Inactive from Ext. Osc. Stable ORS T Minimum Reset Pulse Width RES T Reset Inactive from Standby Inactive STR T Reset Rise ...
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Table 3-10: AC Timing Characteristics - PCI Bus Frame (CLK=33MHz) Symbol Parameter T FRAME# Setup to CLK FRS T C/BE#[3:0] (Bus CMD) Setup to CLK CMS T C/BE#[3:0] (Bus CMD) Hold from CLK CMH T C/BE#[3:0] (Byte Enable) Setup ...
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Table 3-11: AC Timing Characteristics - PCI Bus Stop (CLK=33MHz) Symbol Parameter T STOP# High Z to High from CLK SZH T STOP# Active from CLK SHL T STOP# Inactive from CLK SLH T STOP# High before High Z SHZ ...
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Table 3-12: AC Timing Characteristics BIOS ROM Symbol Parameter T ROMOE# Active from CLK ROE T Slowest Permissible BIOS ROM Access Speed ROM Note: PCI BIOS ROM timing is derived from the 33 MHz PCI bus clock. AGP BIOS ...
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Table 3-13: AC Timing Characteristics - Video Data Port Symbol Parameter T VP0 - VP15 (Incoming Data) Setup VPS T VP0 - VP15 (Incoming Data) Hold VPH T HREF (Incoming HS) Setup HRS T HREF (Incoming HS) Hold HRH T ...
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Table 3-14: AC Timing Characteristics - Panel Output Timing Symbol Parameter T SHFCLK cycle time SCLK T DE and P[35:0] Output Valid Delay DOVD T LP and FLM Output Valid Delay COVD SHFCLK Duty Cycle Note: AC Timing is ...
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Table 3-15: AC Timing Characteristics - A.G. Timing Parameters Symbol Parameter Output Timing T AD[31:0] (Data) Valid from CLK DAD T TRDY# High Z to High from CLK TZH T TRDY# Active from CLK THL T TRDY# Inactive ...
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Databook Electrical Specifications Subject to Change Without Notice Revision 1.3 8/31/98 ...
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Chapter 4 Mechanical Specifications Top View 27 ± 0.1 mm (1.063 ± 0.004" Bottom View 27 ± 0.1 mm (1.063 ...
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+/- Figure 4-2: 256 Ball - Mini Ball Grid ...
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Chapter 5 I/O and Memory Address Maps An extensive set of registers normally controls the graphics system. These registers are a combination of registers defined by IBM when the Video Graphics Array (VGA) was first introduced, and others that have ...
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Address Maps for Going Beyond VGA This graphics controller improves upon VGA by providing additional features that are used through numerous additional registers. Many of these additional registers are simply added to the sub-addressing schemes already defined in the ...
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PCI Configuration Registers Configuration Name Space Offset 00 VENDID 02 DEVID 04 DEVCTL 06 DEVSTAT 08 REV 09 PRG 0A SUB 0B BASE MBASE SUBVENDID 2E SUBDEVID 30 ...
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I/O and Sub-Addressed Register Map Memory I/O Address Read Offset 3B0-3B3 3B4 0x400768 CRTC Index (MDA Emulation) 3B5 0x400769 CRTC Data Port (MDA Emulation) 3B6-3B9 Input Status Register 1 (ST01) 3BA 0x400774 (MDA Emulation) 3BB-3BF 3C0 0x400780 Attribute Controller ...
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Sub-Addressing Indexes and Data Ports Index Port Data Port Addresses Addresses I/O 3C0 I/O 3C0/3C1 Mem 0x400780 Mem 0x400780/781 I/O 3C4 I/O 3C5 Mem 0x400788 Mem 0x400789 I/O 3CE I/O 3CF Mem 0x40079C Mem 0x40079D I/O 3D0 I/O 3D1 Mem ...
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Lower Memory Map Address Range Function A0000-AFFFF VGA Frame Buffer B0000-B7FFF MDA Emulation Character Buffer B8000-BFFFF CGA Emulation Frame Buffer C0000-C7FFF or VGA BIOS ROM C0000 up to CFFFF &+,36 69000 Databook I/O and Memory Address Maps Subject to ...
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Upper Memory Map Size 2MB 2MB 2KB 8MB 4MB 62KB 16MB 64KB 3968KB 2MB 2MB 8MB 64KB 4MB 64KB 3968KB &+,36 69000 Databook I/O and Memory Address Maps Memory Offset 0x000000 to Linear Frame Buffer 0x1FFFFF 0x200000 to 0x3FFFFF 0x400000 ...
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Databook I/O and Memory Address Maps Subject to Change Without Notice Revision 1.3 8/31/98 ...
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Chapter 6 Register Summaries Table 6-1 PCI Configuration Registers Configuration Name Space Offset 00 VENDID 02 DEVID 04 DEVCTL 06 DEVSTAT 08 REV 09 PRG 0A SUB 0B BASE MBASE ...
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Table 6-3: CRT Controller Registers Name CR00 Horizontal Total Register CR01 Horizontal Display Enable End Register CR02 Horizontal Blanking Start Register CR03 Horizontal Blanking End Register CR04 Horizontal Sync Start Register CR05 Horizontal Sync End Register CR06 Vertical Total ...
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Table 6-4: Sequencer Registers Name SR00 Reset Register SR01 Clocking Mode Register SR02 Map Mask Register SR03 Character Map Select Register SR04 Memory Mode Register SR07 Horizontal Character Counter Reset Register Table 6-5: Graphics Controller Registers Name GR00 Set/Reset Register ...
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Table 6-8: Extension Registers Name XR00 Vendor ID Low Register XR01 Vendor ID High Register XR02 Device ID Low Register XR03 Device ID High Register XR04 Revision ID Register XR05 Linear Base Address Low Register XR06 Linear Base Address ...
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Table 6-8: Extension Registers (continued) Name XRA0 Cursor 1 Control Register XRA1 Cursor 1 Vertical Extension Register XRA2 Cursor 1 Base Address Low Register XRA3 Cursor 1 Base Address High Register XRA4 Cursor 1 X-Position Low Register XRA5 Cursor 1 ...
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Table 6-9: Flat Panel Registers Name Register Function FR00 Feature Register FR01 CRT / FP Control Register FR02 FP Mode Control Register FR03 FP Dot Clock Source Register FR04 Panel Power Sequencing Delay Register FR05 Power Down Control 1 ...
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Table 6-10: Multimedia Registers Name Register Function MR00 Module Capability Register MR01 Secondary Capability Register MR02 Capture Control 1 Register MR03 Capture Control 2 Register MR04 Capture Control 3 Register MR05 Capture Control 4 Register MR06-08 Capture Memory Address PTR1 ...
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Table 6-11: BitBLT Registers Name Function BR00 Source and Destination Offset Register BR01 Pattern/Source Expansion Background Color Register BR02 Pattern/Source Expansion Foreground Color Register BR03 Monochrome Source Control Register BR04 BitBLT Control Register BR05 Pattern Address Register BR06 Source ...
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Chapter 7 PCI Configuration Registers Table 7-1 PCI Configuration Registers Configuration Name Space Offset 00 VENDID 02 DEVID 04 DEVCTL 06 DEVSTAT 08 REV 09 PRG 0A SUB 0B BASE MBASE ...
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VENDID Vendor ID Register read-only at PCI configuration offset 00h byte or word accessible accessible only via PCI configuration cycles 15-0 Vendor ID This is the vendor ID assigned to CHIPS by the PCI ...
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DEVCTL Device Control Register read/write at PCI configuration offset 04h byte or word accessible accessible only via PCI configuration cycles Reserved (0000:00) 15-10 Reserved Each of these bits always return a value of 0 when ...
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VGA Palette Snoop 0: Accesses to all VGA I/O locations including those for the palette will be claimed. All read and write accesses to the palette will be performed normally. This is the default after reset. 1: Accesses ...
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DEVSTAT Device Status Register read/write at PCI configuration offset 06h byte or word accessible accessible only via PCI configuration cycles Det Signal Rcvd Rcvd Signal Parity System Master Target Target Error Error Abort Abort Abort ...
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DEVSEL# Timing These two bits specify the longest-possible amount of time that the 69000 will take in decoding an address and asserting DEVSEL#. These two bits always return a value of 01, indicating a medium- length timing. 8 ...
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REV Revision ID Register read-only at PCI configuration offset 08h byte accessible accessible only via PCI configuration cycles Chip Manufacturing Code (xxxx) Note: This register is identical to the Revision ID Register (XR04). 7-4 Chip Manufacturing Code ...
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SUB Sub-Class Code Register read-only at PCI configuration offset 0Ah byte accessible accessible only via PCI configuration cycles 7-0 Sub-Class Code This register always returns a value of 00h to identify this PCI device as a ...
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HDR Header Type Register read-only at PCI configuration offset 0Eh byte accessible accessible only via PCI configuration cycles Single/Multi Function Dev (0) 7 Single/Multiple Function Device This bit always returns a value of 0 when read, indicating ...
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MBASE Memory Base Address Register read/write at PCI configuration offset 10h byte, word, or doubleword accessible accessible only via PCI configuration cycles Memory Space Base Address (0000:0000 Memory Space ...
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SUBVENDID Subsystem Vendor ID Register read-only at PCI configuration offset 2Ch byte or word accessible accessible only via PCI configuration cycles 15-0 Subsystem Vendor ID These bits are intended to carry the vendor ID of ...
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INTLINE Interrupt Line Register read/write at PCI configuration offset 3Ch byte accessible accessible only via PCI configuration cycles 7-0 Interrupt Line This register carries the level number of the interrupt line to which the interrupt output ...
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RBASE ROM Base Address Register read/write at PCI configuration offset 30h byte, word, or doubleword accessible accessible only via PCI configuration cycles ROM Space Base Address 31-18 ROM Space Base ...
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SUBVENDSET Subsystem Vendor ID Set Register read/write at PCI configuration offset 6Ch byte or word accessible accessible only via PCI configuration cycles 15-0 Subsystem Vendor ID Set These bits are used to program the ...
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General Control and Status Registers Chapter 8 General Control and Status Registers These are direct-access registers -- they are NOT read from or written to using any form of sub-indexing scheme. Name ST00 Input Status Register 0 ST01 Input Status ...
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General Control and Status Registers ST00 Input Status Register 0 read-only at I/O Address 3C2h Vert Ret Reserved Interrupt 7 Vertical Retrace Interrupt 0: Indicates that a vertical retrace interrupt is not pending. 1: Indicates that ...
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General Control and Status Registers ST01 Input Status Register 1 read-only at I/O Address 3BAh/3DAh VSYNC Reserved Video Feedback 1,0 Output 7 VSYNC Output 0: The VSYNC output pin is currently inactive. 1: The VSYNC output pin ...
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General Control and Status Registers FCR Feature Control Register write at I/O Address 3BAh/3DAh read at I/O Address 3CAh Reserved 7-4 Reserved These bits return the value of 0 when read. 3 VSYNC Control 0: VSYNC ...
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General Control and Status Registers MSR Miscellaneous Output Register write at I/O Address 3C2h read at I/O Address 3CCh Sync Output Polarity Page Select (00) (0) 7-6 Sync Output Polarity Bit 7 controls the polarity of the ...
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General Control and Status Registers 3-2 Clock Select These two bits select the dot clock. Bit Selected Clock 3 2 CLK0 -- default 25MHz 0 0 (for standard VGA modes with a horizontal resolution of 320 or 640 pixels. ...
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Chapter 10 Sequencer Registers Name SR00 Reset Register SR01 Clocking Mode Register SR02 Plane Mask Register SR03 Character Map Select Register SR04 Memory Mode Register SR07 Horizontal Character Counter Reset Register The sequencer registers are accessed by writing the index ...
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Chapter 9 CRT Controller Registers Name CR00 Horizontal Total Register CR01 Horizontal Display Enable End Register CR02 Horizontal Blanking Start Register CR03 Horizontal Blanking End Register CR04 Horizontal Sync Start Register CR05 Horizontal Sync End Register CR06 Vertical Total Register ...
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The CRT controller registers are accessed by writing the index of the desired register into the CRT Controller Index Register at I/O address 3B4h or 3D4h (depending upon whether the graphics system is configured for MDA or CGA emulation), ...
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CR00 Horizontal Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 00h 7-0 Horizontal Total These bits provide either all 8 bits of an 8-bit value or the least significant 8 bits ...
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CR03 Horizontal Blanking End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 03h Reserved Display Enable Skew Control 7 Reserved Values written to this bit are ignored. To maintain consistency with ...
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CR04 Horizontal Sync Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 04h 7-0 Horizontal Sync Start This register is used to specify the beginning of the horizontal sync pulse relative to ...
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CR05 Horizontal Sync End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 05h Hor Blnk End Horizontal Sync Delay Bit 5 7 Horizontal Blanking End Bit 5 This bit provides either ...
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CR06 Vertical Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 06h 7-0 Vertical Total Bits These bits provide the 8 least significant bits of either a 10-bit or 12-bit value that ...
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CR07 Overflow Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 07h Vert Sync Vert Disp En Vert Total Bit Start Bit 9 Bit Vertical Sync Start Bit 9 ...
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Vertical Total Bit 9 The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes the scanlines both inside and outside of the active display area. In standard VGA modes, where bit ...
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Vertical Blanking Start Bit 8 The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where ...
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Vertical Display Enable End Bit 8 The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last scanline within the active display area. In standard VGA modes, where bit 0 of the ...
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CR08 Preset Row Scan Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 08h Reserved Left Hor Pixel Shift 7 Reserved 6-5 Leftward Horizontal Pixel Shift Bits 6 and 5 of this ...
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CR09 Maximum Scanline Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 09h Double Line Cmp Vert Blnk Scanning Bit 9 Start Bit 9 7 Double Scanning 0: Disables double scanning. The clock ...
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Vertical Blanking Start Bit 9 The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where ...
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CR0A Text Cursor Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Ah Text Cursor Reserved Off This cursor is the text cursor that is part of the VGA standard and should ...
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CR0B Text Cursor End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Bh Reserved Text Cursor Skew This cursor is the text cursor that is part of the VGA standard and ...
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CR0C Start Address High Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Ch 7-0 Start Address Bits 15-8 This register provides bits 15 through 8 of either a 16-bit or 20-bit value ...
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CR0D Start Address Low Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Dh 7-0 Start Address Bits 7-0 This register provides the eight least significant bits of either a 16-bit or ...
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CR0E Text Cursor Location High Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Eh This cursor is the text cursor that is part of the VGA standard and should not be confused ...
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CR10 Vertical Sync Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 10h 7-0 Vertical Sync Start Bits 7-0 This register provides the 8 least significant bits of either a 10-bit ...
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CR11 Vertical Sync End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 11h Protect Regs Vert Int Reserved 0-7 Enable 7 Protect Registers 0-7 0: Enable writes to registers CR00-CR07. 1: Disable ...
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CR12 Vertical Display Enable End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 12h 7-0 Vertical Display Enable End Bits 7-0 This register provides the 8 least significant bits of either ...
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CR14 Underline Location Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 14h Reserved Dword Mode Count Reserved 6 Doubleword Mode 0: Frame buffer addresses are interpreted by the frame ...
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CR15 Vertical Blanking Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 15h 7-0 Vertical Blanking Start Bits 7-0 This register provides the 8 least significant bits of either a 10-bit ...
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CR17 CRT Mode Control read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 17h CRT Ctrl Word or Byte Address Reset Mode Wrap 7 CRT Controller Reset 0: Forces horizontal and vertical sync signals ...
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Count The memory address counter is incremented either every character clock or every 4 character clocks, depending upon the setting of bit 5 of the Underline Location Register. 1: The memory address counter is incremented ...
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Bits Generated by the Memory Address Counter (MAOut0 to MAOut15) Byte Mode Word Mode CR14 bit 6=0 CR14 bit 6=0 CR17 bit 6=1 CR17 bit 6=0 CR17 bit 5=X CR17 bit 5=1 MAOut0 MAOut15 MAOut1 MAOut0 MAOut2 MAOut1 MAOut3 MAOut2 ...
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CR18 Line Compare Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 18h 7-0 Line Compare Bits 7-0 This register provides the 8 least significant bits of a 10-bit value that specifies ...
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CR30 Extended Vertical Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 30h Reserved 7-4 Reserved These bits should always be written with the value of 0. 3-0 Vertical Total Bits 11-8 ...
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CR32 Extended Vertical Sync Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 32h Reserved 7-4 Reserved These bits should always be written with the value of 0. 3-0 Vertical Sync ...
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CR33 Extended Vertical Blanking Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 33h Reserved 7-4 Reserved These bits should always be written with the value of 0. 3-0 Vertical Blanking Start ...
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CR38 Extended Horizontal Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 38h 7-1 Reserved These bits should always be written with the value Horizontal Total Bit 8 ...
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CR3C Extended Horizontal Blanking End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 3Ch Horizontal Blank End Bits 7 and 6 (00) 7-6 Horizontal Blanking End Bits 7 and 6 The horizontal ...
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CR40 Extended Start Address Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 40h Strt Addr En Reserved 7 Extended Mode Start Address Enable This bit is used only in extended modes, ...
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CR41 Extended Offset Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 41h Reserved 7-4 Reserved Whenever this register is written to, these bits should be set to 0. 3-0 Offset Bits 11-8 ...
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CR71 NTSC/PAL Video Output Control Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 71h NTSC/ PAL Pedestal Blanking Sel Enable Delay Ctrl 7 NTSC/PAL Select 0: Selects NTSC-formatted video output. 1: ...
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CR72 NTSC/PAL Horizontal Serration 1 Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 72h 7-0 Horizontal Serration 1 Start These 8 bits specify the start position along the length of a ...
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CR74 NTSC/PAL Horizontal Pulse Width Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 74h Reserved Round Off 7-6 Reserved 5 NTSC/PAL Horizontal Pulse Width Round Off Control 0: Enables the generation ...
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CR75 NTSC/PAL Filtering Burst Read Length Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 75h Reserved (Writable) (xxxx) 7-4 Reserved These bits should always be written with the value of 0. 3-0 ...
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CR77 NTSC/PAL Filtering Control Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 77h Text Mode Reserved (Writable) Line Halving (0) (000) 7 VGA Text Mode Scanline Halving 0: Disables VGA text ...
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CR78 NTSC/PAL Vertical Reduction Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 78h Vertical Reserved Reserved Redux En (0) (0) (0) 7 Vertical Reduction Enable 0: Vertcal reduction is disabled. This is ...
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CR79 NTSC/PAL Horizontal Total Fine Adjust Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 79h Reserved (Writable) (0000:0) 7-3 Reserved 2-0 Horizontal Total Fine Adjust These 3 bits can be use ...
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Chapter 10 Sequencer Registers Name SR00 Reset Register SR01 Clocking Mode Register SR02 Plane Mask Register SR03 Character Map Select Register SR04 Memory Mode Register SR07 Horizontal Character Counter Reset Register The sequencer registers are accessed by writing the index ...
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SRX Sequencer Index Register read/write at I/O address 3C4h This register is cleared to 00h by reset Reserved 7-3 Reserved 2-0 Sequencer Register Index These three bits are used to select any one of the sequencer ...
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SR01 Clocking Mode Register read/write at I/O address 3C5h with index at address 3C4h set to 01h Reserved Screen Off 7-6 Reserved 5 Screen Off 0: Permits normal operation 1: Disables all graphics output except for video ...
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SR02 Plane Mask Register read/write at I/O address 3C5h with index at address 3C4h set to 02h Reserved Note: This register is referred to in the VGA standard as the Map Mask Register. However, the word ...
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SR03 Character Map Select Register read/write at I/O address 3C5h with index at address 3C4h set to 03h Char Map A Reserved Select (bit 0) Note: In text modes, bit 3 of the video data’s attribute byte ...
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SR04 Memory Mode Register read/write at I/O address 3C5h with index at address 3C4h set to 04h Reserved 7-4 Reserved 3 Chain 4 Mode 0: The manner in which the frame buffer memory is mapped is ...
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SR07 Horizontal Character Counter Reset Register read/write at I/O address 3C5h with index at address 3C4h set to index 07h Writing this register with any data will cause the horizontal character counter to be held in reset ...
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Databook Sequencer Registers Subject to Change Without Notice Revision 1.3 8/31/98 ...
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Chapter 11 Graphics Controller Registers Name Function GR00 Set/Reset Register GR01 Enable Set/Reset Register GR02 Color Compare Register GR03 Data Rotate Register GR04 Read Map Select Register GR05 Graphics Mode Register GR06 Miscellaneous Register GR07 Color Don’t Care Register GR08 ...
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GRX Graphics Controller Index Register read/write at I/O address 3CEh This register is cleared to 00h by reset Reserved 7-4 Reserved 3-0 Graphics Controller Register Index These four bits are used to select any one of ...
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GR01 Enable Set/Reset Register read/write at I/O address 3CFh with index at address 3CEh set to 01h Reserved 7-4 Reserved 3-0 Enable Set/Reset Plane 3 through Enable Set/Reset Plane 0 0: The corresponding memory plane can be ...
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GR03 Data Rotate Register read/write at I/O address 3CFh with index at address 3CEh set to 03h Reserved 7-5 Reserved 4-3 Function Select These bits specify the logical function (if any performed on data ...
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GR04 Read Plane Select Register read/write at I/O address 3CFh with index at address 3CEh set to 04h 7-2 Reserved 1-0 Read Plane Select These two bits select the memory plane from which the CPU reads data ...
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GR05 Graphics Mode Register read/write at I/O address 3CFh with index at address 3CEh set to 05h Reserved Shift Register Control 7 Reserved 6-5 Shift Register Control In standard VGA modes, pixel data is transferred from ...
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Four bits of data at a time from parallel bytes in each of the 4 memory planes are transferred to the palette in a pattern that iterates per byte through memory planes 0 through 3. First the 4 ...
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Read Mode 0: During a CPU read from the frame buffer, the value returned to the CPU is data from the memory plane selected by bits 1 and 0 of the Read Plane Select Register (GR04). 1: During ...
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GR06 Miscellaneous Register read/write at I/O address 3CFh with index at address 3CEh set to 06h Reserved 7-4 Reserved 3-2 Memory Map Mode These 2 bits control the mapping of the frame buffer into the CPU address ...
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GR07 Color Don’t Care Register read/write at I/O address 3CFh with index at address 3CEh set to 07h Reserved 7-4 Reserved 3-0 Ignore Color Plane 3 through Ignore Color Plane 0 0: The corresponding bit in ...
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Chapter 12 Attribute Controller Registers Name Function AR00-AR0F Color Data Registers AR10 Mode Control Register AR11 Overscan Color Register AR12 Memory Plane Enable Register AR13 Horizontal Pixel Panning Register AR14 Color Select Register Unlike the other sets of indexed registers, ...
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ARX Attribute Controller Index Register read/write at I/O address 3C0h Video Reserved Enable Note: AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words “plane,” “color plane,” “display memory plane,” ...
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AR10 Mode Control Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 10h Palette Bits Pixel Pixel Width/ P5, P4 Panning Clk Select Select Compat 7 Palette Bits ...
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Enable Line Graphics Character Code 0: Every 9th pixel of a horizontal line (i.e., the last pixel of each horizontal line of each 9- pixel wide character box) is assigned the same attributes as the background of the ...
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AR12 Memory Plane Enable Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 12h Reserved Video Status Mux Note: AR12 is referred to in the VGA standard as ...
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AR13 Horizontal Pixel Panning Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 13h Reserved 7-4 Reserved 3-0 Horizontal Pixel Shift Bits 3-0 of this register hold ...
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AR14 Color Select Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 14h Reserved 7-4 Reserved 3-2 Palette Bits P7 and P6 These are the 2 upper-most of ...
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Databook Attribute Controller Registers Subject to Change Without Notice Revision 1.3 8/31/98 ...
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Chapter 13 Palette Registers Name Function PALMASK Palette Data Mask Register PALSTATE Palette State Register PALRX Palette Read Index Register PALWX Palette Write Index Register PALDATA Palette Data Register Background: The original VGA graphics system and earlier compatible ones had ...
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Accessing Color Data Locations Within the Palette A complex sub-indexing scheme using separate read and write access indices and a data port is used to access both the standard and alternate palette locations within the palette where color data ...
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PALMASK Palette Data Mask Register read/write at I/O address 3C6h 7-0 Pixel Data Mask In indexed-color mode, the 8 bits of this register are logically ANDed with the 8 bits of pixel data received from the frame ...
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PALRX Palette Read Index Register write-only at I/O address 3C7h 7-0 Palette Read Index This 8-bit value is an index that selects 1 of the 256 standard locations within the palette ( alternate ...
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PALDATA Palette Data Register read/write at I/O address 3C9h 7-0 Palette Data Register This byte-wide data port provides read or write access to the three bytes of data carried by palette location selected using the Palette Read ...
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Databook Palette Registers Subject to Change Without Notice Revision 1.3 8/31/98 ...
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Chapter 14 Extension Registers Name XR00 Vendor ID Low Register XR01 Vendor ID High Register XR02 Device ID Low Register XR03 Device ID High Register XR04 Revision ID Register XR05 Linear Base Address Low Register XR06 Linear Base Address High ...
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Name XRA0 Cursor 1 Control Register XRA1 Cursor 1 Vertical Extension Register XRA2 Cursor 1 Base Address Low Register XRA3 Cursor 1 Base Address High Register XRA4 Cursor 1 X-Position Low Register XRA5 Cursor 1 X-Position High Register XRA6 ...
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XRX Extension Register Index Register read/write at I/O address 3D6h This register is cleared to 00h by reset 7-0 Extension Register Index These 8 bits are used to select any one of the extension registers to be ...
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XR01 Vendor ID High Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 01h 7-0 Vendor ID Bits 15-8 These 8 bits always carry the value 10h. This is the upper ...
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XR03 Device ID High Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 03h 7-0 Device ID High These bits always carry the value 00h. This is the upper byte of CHIPS’ ...
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XR05 Linear Base Address Low Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 05h Mem Space Base Bit 23 (0) 7 Memory Space Base Address Bit 23 This bit is ...
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XR08 Host Bus Configuration Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 08h 7-2 Reserved These bits always return the value of 0 when read. 1 PCI VGA Address Decode Enable ...
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XR09 I/O Control Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 09h 7-2 Reserved These bits always return the value of 0 when read. 1 Attribute Controller Extensions Enable 0: ...
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XR0A Frame Buffer Mapping Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Ah Reserved Endian Byte Swapping (00) 7-6 Reserved These bits always return the value of 0 when read. 5-4 ...
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Planar to Non-Planar Address Translation Enable This bit provides a single-bit switch that can be used to alter the manner in which the frame buffer memory appears from the perspective of the host bus to be organized so ...
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XR0B PCI Burst Write Support Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Bh Reserved (0000) 7-4 Reserved These bits always return the value of 0 when read. 3 Font Expansion ...
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XR0E Frame Buffer Page Select Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Eh Reserved (0) :7 Reserved This bit always returns the value of 0 when read. 6-0 Page ...
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XR20 BitBLT Configuration Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 20h Reserved BitBLT Engine (00) 7-6 Reserved These bits always have the value of 0 when read. 5-4 BitBLT Engine ...
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XR40 Memory Access Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 40h Reserved (Writable) 7-2 Reserved (Writable) These bits should always be set to the value ...
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XR60 Video Pin Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 60h Reserved PCLK Pin Source (0) (0) 7 Reserved This bit always returns the value of 0 when read. ...
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XR61 DPMS Sync Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 61h Reserved DPMS DPMS VSYNC HSYNC (0) (0) (0) 7 Reserved This bit always has the value of ...
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XR62 GPIO Pin Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 62h GPIO7 Reserved Direction (0) (00) Note: See the FP Pin Control 2 Register (FR0C) for direction control of ...
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XR63 GPIO Pin Data Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 63h GPIO7 Data Reserved (x) (00) 7 GPIO7 Data This bit is used in either reading or setting ...
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XR67 Pin Tri-State Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 67h 7-2 Reserved These bits always return the value of 0 when read. 1 Video Data Port Tri-State 0: ...
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XR70 Configuration Pins 0 Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 70h CFG7 CFG6 CFG5 (x) (x) (x) The bits of this register indicate the state of each of ...
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Pin CFG3 Reserved. No interpretation has yet been assigned to the state of this bit, and the hardware does not interpret the state of the corresponding pin during reset. 2 Pin CFG2 Reserved. No interpretation has yet been assigned ...
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XR71 Configuration Pins 1 Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 71h CFG15 CFG14 CFG13 (x) (x) (x) The bits of this register indicate the state of each of ...
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XR80 Pixel Pipeline Configuration 0 Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 80h 6-Bit/8-Bit Reserved Pixel DAC Select Averaging (0) (0) (0) 7 6-Bit/8-Bit DAC Select 0: All three D-to-A ...
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CRT Overscan Enable 0: Disable the use of the CRT overscan color (Overscan, bit 0). This is the default after reset. 1: Enable the use of the CRT overscan color (Overscan, bit 0). 0 Palette Addressing Select 0: ...
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XR81 Pixel Pipeline Configuration 1 Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 81h Reserved (000) 7-5 Reserved These bits always return the value of 0 when read. 4 VGA Standard ...
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XR82 Pixel Pipeline Configuration 2 Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 82h Reserved (0000) 7-4 Reserved These bits always return the value of 0 when read. 3 Graphics ...
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XRA0 Cursor 1 Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to A0h Cursor 1 Cursor 1 Cursor 1 Blink En V Stretch H Stretch (0) (0) (0) 7 Cursor 1 ...
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XRA1 Cursor 1 Vertical Extension Register read/write at I/O address 3D7h with index at I/O address 3D6h set to A1h 7-0 Cursor 1 Vertical Extension When the vertical extension feature for cursor 1 is enabled by ...
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XRA3 Cursor 1 Base Address High Register read/write at I/O address 3D7h with index at I/O address 3D6h set to A3h Reserved (00) 7-6 Reserved These bits always return the value of 0 when read. 5-0 Cursor ...
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XRA5 Cursor 1 X-Position High Register read/write at I/O address 3D7h with index at I/O address 3D6h set to A5h X-Pos Sign Bit (0) 7 Cursor 1 X-Position Sign Bit This bit provides the sign bit ...
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XRA7 Cursor 1 Y-Position High Register read/write at I/O address 3D7h with index at I/O address 3D6h set to A7h Y-Pos Sign Bit (0) 7 Cursor 1 Y-Position Sign Bit This bit provides the sign bit of ...
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XRA8 Cursor 2 Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to A8h Cursor 2 Cursor 2 Cursor 2 Blink En V Stretch H Stretch (0) (0) (0) 7 Cursor ...
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XRA9 Cursor 2 Vertical Extension Register read/write at I/O address 3D7h with index at I/O address 3D6h set to A9h 7-0 Cursor 2 Vertical Extension When the vertical extension feature for cursor 2 is enabled by setting ...