MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 85

• Manufacturer Part Number: MT48LC16M16A2P-75:DTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16A2P-75:DTR

• Lead Free Status / Rohs Status: Compliant

Clock Suspend
Figure 54: Clock Suspend During WRITE Burst
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Command
Internal
Address
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls when an in-
ternal clock edge is suspended will be ignored; any data present on the DQ balls
remains driven; and burst counters are not incremented, as long as the clock is suspended.
Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-
tion will resume on the subsequent positive clock edge.
clock
1. For this example, BL = 4 or greater, and DQM is LOW.
CKE
CLK
D
IN
NOP
T0
WRITE
Bank,
Col n
D
T1
IN
T2
85
T3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
D
T4
IN
256Mb: x4, x8, x16 SDRAM
Don’t Care
T5
NOP
D
IN
© 1999 Micron Technology, Inc. All rights reserved.
Clock Suspend