MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 80

• Manufacturer Part Number: MT48LC16M16A2P-75:DTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16A2P-75:DTR

• Lead Free Status / Rohs Status: Compliant

AUTO REFRESH Operation
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
The AUTO REFRESH command is used during normal operation of the device to refresh
the contents of the array. This command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be precharged prior to issuing an AUTO
REFRESH command. The AUTO REFRESH command should not be issued until the min-
imum
internal refresh controller. This makes the address bits “Don’t Care” during an AUTO
REFRESH command.
After the AUTO REFRESH command is initiated, it must not be interrupted by any exe-
cutable command until
NOP commands must be issued on each positive edge of the clock. The SDRAM re-
quires that every row be refreshed each
REFRESH command—calculated by dividing the refresh period (
rows to be refreshed—meets the timing requirement and ensures that each row is re-
freshed. Alternatively, to satisfy the refresh requirement a burst refresh can be em-
ployed after every
the number of rows to be refreshed at the minimum cycle rate (
t
RP is met following the PRECHARGE command. Addressing is generated by the
t
REF period by issuing consecutive AUTO REFRESH commands for
t
RFC has been met. During
80
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
REF period. Providing a distributed AUTO
256Mb: x4, x8, x16 SDRAM
t
RFC time, COMMAND INHIBIT or
AUTO REFRESH Operation
© 1999 Micron Technology, Inc. All rights reserved.
t
RFC).
t
REF) by the number of