MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 52

• Manufacturer Part Number: MT48LC16M16A2P-75:DTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16A2P-75:DTR

• Lead Free Status / Rohs Status: Compliant

Figure 21: Consecutive READ Bursts
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Command
Command
Address
Address
1. Each READ command can be issued to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
T0
Bank,
READ
READ
Col n
Bank,
Col n
CL = 2
CL = 3
T1
T1
NOP
NOP
52
T2
T2
NOP
NOP
D
OUT
n
T3
T3
NOP
NOP
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D
D
n + 1
OUT
OUT
READ
T4
READ
T4
Bank,
Bank,
Col b
Col b
X = 1 cycle
D
n + 2
D
Transitioning data
OUT
OUT
256Mb: x4, x8, x16 SDRAM
X = 2 cycles
T5
T5
NOP
NOP
D
D
n + 3
OUT
OUT
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T6
T6
NOP
NOP
READ Operation
D
D
OUT
OUT
b
Don’t Care
T7
NOP
D
OUT