MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 44

• Manufacturer Part Number: MT48LC16M16A2P-75:DTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16A2P-75:DTR

• Lead Free Status / Rohs Status: Compliant

Figure 17: Initialize and Load Mode Register
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
DQML, DQMU
COMMAND
BA0, BA1
A[12:11]
A[9:0],
DQM/
CKE
A10
DQ
CK
T = 100µs
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Power-up:
V
CLK stable
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MIN
DD
and
t CKS
t CMS
T0
NOP
Notes:
t CKH
High-Z
t CMH
SINGLE BANK
ALL BANKS
t CK
PRECHARGE
1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at
BANKS
T1
ALL
t RP
Precharge
all banks
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Tn + 1
REFRESH
AUTO
t CH
AUTO REFRESH
t RFC
NOP
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NOP
t
P + 1.
44
t CL
To + 1
REFRESH
AUTO
AUTO REFRESH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t RFC
NOP
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NOP
256Mb: x4, x8, x16 SDRAM
t AS
t AS
LOAD MODE
Tp + 1
REGISTER
CODE
CODE
t AH
t AH
Program Mode Register
5
© 1999 Micron Technology, Inc. All rights reserved.
t MRD
Tp + 2
NOP
Initialization
1, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE
UNDEFINED