N25Q128A13ESF40F NUMONYX, N25Q128A13ESF40F Datasheet - Page 84

• Manufacturer Part Number: N25Q128A13ESF40F
• Description: NUMN25Q128A13ESF40F 128MB SPI FLASH MEMO
• Manufacturer: NUMONYX

9.1.6
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DQ0
DQ0
DQ1
DQ1
C
S
C
S
Mode 3
Mode 0
Figure 14. Dual I/O Fast Read instruction sequence
Quad Output Fast Read
The Quad Output Fast Read (QOFR) instruction is very similar to the Dual Output Fast
Read (DOFR) instruction, except that the data are shifted out on four pins (pin DQ0, pin
DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1) instead of only two. Outputting the data on
four pins instead of one doubles the data transfer bandwidth compared to the Dual Output
Fast Read (DOFR) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Quad
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin
HOLD/DQ3 (1) at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 15.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on pin DQ0, pin DQ1, pin
W/VPP/DQ2 and pin HOLD/DQ3 (1). The whole memory can, therefore, be read with a
single Quad Output Fast Read (QOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
23 24 25
IO switches from Input to Output
6
7
Byte 1
4
5
0
26
2
3
1
27 28 29 30 31 32 33 34 35 36 37
0
1
2
Instruction
6
7
3
Byte 2
4
5
4
2
3
5
0
1
6
6
7
7
4
5
Byte 3
7
6
8
2
3
4
5
9 10 11 12 13 14
0
1
2
3
6
7
0
1
4
Byte 4
5
6
7
Address
38
2
3
4
5
39
0
1
2
3
6
7
15 16 17 18 19 20
0
1
6
7
4
5
2
3
0
1
Dummy Cycles
Dual_IO_Fast_Read